Testing retention flip-flops in power-gated designs

This paper focuses on tackling two problems on testing retention flip-flops in power-gated designs. The first one is how to reduce the virtual-V DD discharge time after entering the sleep mode. The second one is how to avoid the test escape caused by the unintended initial value of the retention fli...

Full description

Saved in:
Bibliographic Details
Main Authors: Hao-Wen Hsu, Shih-Hua Kuo, Wen-Hsiang Chang, Shi-Hao Chen, Ming-Tung Chang, Chao, Mango C.-T
Format: Conference Proceeding
Language:English
Subjects:
Automatic test pattern generation
Capacitance
Discharges (electric)
Equations
Logic gates
Mathematical model
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper focuses on tackling two problems on testing retention flip-flops in power-gated designs. The first one is how to reduce the virtual-V DD discharge time after entering the sleep mode. The second one is how to avoid the test escape caused by the unintended initial value of the retention flip-flop during the restore function. To solve the first problem, we propose a novel ATPG framework to generate repeatedly toggling pattern pairs that can create maximal virtual-V DD drop for a cycle. To solve the second problem, we propose a new test procedure to avoid the unintended initial value of the retention flip-flop after restoring. The effectiveness of the proposed ATPG framework and the new test procedure will be validated through SPICE simulation based on an industrial MTCMOS cell library.
ISSN:1093-0167
2375-1053
DOI:10.1109/VTS.2013.6548880