On design of priority-driven load-adaptive monitoring-based hardware for managing interrupts in embedded event-triggered real-time systems

The paper details design of a hardware unit for preventing real-time systems from overloads caused by excessive interrupt rates. Novelty of the hardware can be seen in the fact it is able to adapt interrupt service rate to the RT system load and to the actual priority assignment policy. The load is...

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Main Author: Strnadel, J.
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Context
Delays
Field programmable gate arrays
Hardware
Monitoring
Throughput
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description The paper details design of a hardware unit for preventing real-time systems from overloads caused by excessive interrupt rates. Novelty of the hardware can be seen in the fact it is able to adapt interrupt service rate to the RT system load and to the actual priority assignment policy. The load is monitored on basis of special low-overhead signals produced by the system for this purpose. The hardware is designed to pre-process all interrupts before they arrive to the system. Then, the hardware is able to buffer each interrupt-related communication until the system is underloaded or running an activity having a lower priority comparing to the interrupt. Design of the hardware was described in VHDL and synthesized into Xilinx Spartan-6 devices. Details such as buiding blocks, overheads and limits related to the realization are presented in this paper.
doi_str_mv 10.1109/DDECS.2013.6549783
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subjects Computer architecture
Context
Delays
Field programmable gate arrays
Hardware
Monitoring
Throughput
title On design of priority-driven load-adaptive monitoring-based hardware for managing interrupts in embedded event-triggered real-time systems
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