Split ADC background self-calibration of a 16-b successive approximation ADC in 180nm CMOS

A 16-b, 1MSps successive approximation ADC in 180nm CMOS uses the "split ADC" architecture to enable continuous, all-digital, background self-calibration of ADC linearity. Convergence of calibration parameters to noise-limited accuracy is demonstrated with an adaptation time constant less...

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Bibliographic Details
Main Authors: McNeill, John, David, Christopher, Coln, Michael C. W., Ka Yan Chan
Format: Conference Proceeding
Language:English
Subjects:
Accuracy
Algorithm design and analysis
Approximation methods
Calibration
Capacitors
CMOS integrated circuits
Convergence
Online Access:Request full text
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Description
Summary:A 16-b, 1MSps successive approximation ADC in 180nm CMOS uses the "split ADC" architecture to enable continuous, all-digital, background self-calibration of ADC linearity. Convergence of calibration parameters to noise-limited accuracy is demonstrated with an adaptation time constant less than 300ms. In the capacitive DAC, a novel segmentation and shuffling approach is used to mitigate requirements on input signal activity; calibration is possible even in the presence of DC input signals.
ISSN:1091-5281
DOI:10.1109/I2MTC.2013.6555430