A closed-form delay estimation model for current-mode high speed VLSI interconnects

Closed-form model for the delay estimation of current-mode Resistance Inductance Capacitance (RLC) interconnects in VLSI circuits is presented. The existing Eudes model for interconnect transfer function approximation is extended and applied for further accurate estimation of delay. With the equival...

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Bibliographic Details
Main Authors: Kavicharan, M., Murthy, N. S., Rao, N. Bheema
Format: Conference Proceeding
Language:English
Subjects:
Computational modeling
Delay
Eudes model
Load modeling
MacLaurin series
Mathematical model
MATLAB
ramp input
RLC interconnects
SOC
transfer function
transient analysis
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Summary:Closed-form model for the delay estimation of current-mode Resistance Inductance Capacitance (RLC) interconnects in VLSI circuits is presented. The existing Eudes model for interconnect transfer function approximation is extended and applied for further accurate estimation of delay. With the equivalent lossy interconnect transfer function, finite ramp responses are obtained and line delay is estimated for various line lengths, per unit length inductances and load capacitances. The delay values are computed using Eudes model, extended Eudes model and are compared with the HSPICE W-element model. The obtained delay values of existing Eudes model max error percentage is 14.3% whereas our extended Eudes model is in good agreement with those of HSPICE results within 2% for the line lengths of 1mm to 10mm.
DOI:10.1109/TAEECE.2013.6557325