Critical path analysis for primary inputs optimization

Designing of Very Large Scale Integrated (VLSI) portable devices require less power, minimal time to market, high performance in order to achieve reliability and efficiency. The design constraints include speed, area and cost. Hence, the innovative techniques must optimize the above design constrain...

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Bibliographic Details
Main Authors: Premalatha, P., Rajaram, A., Sowmiya, G., Saravanan, S., Vijaysai, R.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Benchmark testing
Circuit faults
Communications technology
Conferences
Critical path
Integrated circuit modeling
Linear Feedback Shift Register
Optimization
Primary input
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Summary:Designing of Very Large Scale Integrated (VLSI) portable devices require less power, minimal time to market, high performance in order to achieve reliability and efficiency. The design constraints include speed, area and cost. Hence, the innovative techniques must optimize the above design constraints. In this work, a new approach is used to find the optimistic primary inputs, which is indirectly used to increase the speed is proposed. Critical path reduction is also achieved. Then the work is extended with the implementation of Linear Feedback Shift Register (LFSR).The independent primary inputs are neglected and only the optimized inputs are considered. The ISCAS 85 benchmark circuits are targeted for the proposed work.
DOI:10.1109/CICT.2013.6558173