Timing analysis and optimization of a high-performance CMOS processor chipset

We describe the timing analysis and optimization methodology used for the chipset inside the IBM S/390 Parallel Enterprise Server-Generation 3. After an introduction to the concepts of static timing analysis, we describe the timing-modeling for the gates and interconnects, explain the optimization s...

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Bibliographic Details
Main Authors: Fassnacht, U., Schietke, J.
Format: Conference Proceeding
Language:English
Subjects:
Analytical models
Clocks
CMOS process
Integrated circuit interconnections
Libraries
Logic
Mathematics
Optimization methods
Testing
Timing
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Summary:We describe the timing analysis and optimization methodology used for the chipset inside the IBM S/390 Parallel Enterprise Server-Generation 3. After an introduction to the concepts of static timing analysis, we describe the timing-modeling for the gates and interconnects, explain the optimization schemes and present obtained results.
DOI:10.1109/DATE.1998.655876