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Fast lossless image compression with Radiation Hardening by hardware/software co-design on platform FPGAs
Motivated by the proposed NASA HyspIRI mission, our work improves existing Radiation Hardening by Software (RHBSW) techniques with FPGA Fabric Checkpoint/Restart (F2CPR) to bring enhanced hardware/software co-designed fault tolerance to commercial FPGA devices. We evaluate our approach on Fast Lossl...
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creator | Schmidt, Andrew G. French, Matthew |
description | Motivated by the proposed NASA HyspIRI mission, our work improves existing Radiation Hardening by Software (RHBSW) techniques with FPGA Fabric Checkpoint/Restart (F2CPR) to bring enhanced hardware/software co-designed fault tolerance to commercial FPGA devices. We evaluate our approach on Fast Lossless (FL) image compression prediction for hyperspectral imagery in order to meet real-time performance requirements that cannot be achieved with aging radiation hardened devices. We report results across several metrics including resource utilization, performance, and an analysis of the vulnerability to Single Event Upsets (SEU) through the use of a hardware based fault injector. Results show low performance overhead (4-8%) achieving a speedup of 11.28× with a hardware accelerated implementation. |
doi_str_mv | 10.1109/ASAP.2013.6567560 |
format | conference_proceeding |
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We evaluate our approach on Fast Lossless (FL) image compression prediction for hyperspectral imagery in order to meet real-time performance requirements that cannot be achieved with aging radiation hardened devices. We report results across several metrics including resource utilization, performance, and an analysis of the vulnerability to Single Event Upsets (SEU) through the use of a hardware based fault injector. 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We evaluate our approach on Fast Lossless (FL) image compression prediction for hyperspectral imagery in order to meet real-time performance requirements that cannot be achieved with aging radiation hardened devices. We report results across several metrics including resource utilization, performance, and an analysis of the vulnerability to Single Event Upsets (SEU) through the use of a hardware based fault injector. Results show low performance overhead (4-8%) achieving a speedup of 11.28× with a hardware accelerated implementation.</description><subject>Fabrics</subject><subject>Fault tolerance</subject><subject>Fault tolerant systems</subject><subject>Field programmable gate arrays</subject><subject>Hardware</subject><subject>Radiation hardening (electronics)</subject><subject>Software</subject><issn>1063-6862</issn><isbn>9781479904945</isbn><isbn>1479904945</isbn><isbn>9781479904938</isbn><isbn>1479904937</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNpVkMtqwzAQRVXaQtM0H1C60Q_YkTSWZC1NaJJCoKHNPkiW5Kj4hWUI-fs6NJuuZg7cOzAHoVdKUkqJWhbfxT5lhEIquJBckDu0UDKnmVSKZAry-3-c8Qc0o0RAInLBntBzjD-EMAkin6Gw1nHEdRdj7WLEodGVw2XX9MOEoWvxOYwn_KVt0OMVt3qwrg1thc0FnyY468EtY-fH6zI1E-tiqFo8Zftaj74bGrzeb4r4gh69rqNb3OYcHdbvh9U22X1uPlbFLglU8jExnGa-tMQCY2C4tmA8LbnNiAejrXLSqNIqSYEBEYZJVnIzSaBAci8FzNHb39ngnDv2w_TRcDneRMEvi1dbaQ</recordid><startdate>201306</startdate><enddate>201306</enddate><creator>Schmidt, Andrew G.</creator><creator>French, Matthew</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201306</creationdate><title>Fast lossless image compression with Radiation Hardening by hardware/software co-design on platform FPGAs</title><author>Schmidt, Andrew G. ; French, Matthew</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-b514fcd0d3223b5ad3bf1c5d40f3bad9e7b9cd97132306b272c5b7561308f763</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Fabrics</topic><topic>Fault tolerance</topic><topic>Fault tolerant systems</topic><topic>Field programmable gate arrays</topic><topic>Hardware</topic><topic>Radiation hardening (electronics)</topic><topic>Software</topic><toplevel>online_resources</toplevel><creatorcontrib>Schmidt, Andrew G.</creatorcontrib><creatorcontrib>French, Matthew</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore Digital Library</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Schmidt, Andrew G.</au><au>French, Matthew</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Fast lossless image compression with Radiation Hardening by hardware/software co-design on platform FPGAs</atitle><btitle>2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors</btitle><stitle>ASAP</stitle><date>2013-06</date><risdate>2013</risdate><spage>103</spage><epage>106</epage><pages>103-106</pages><issn>1063-6862</issn><isbn>9781479904945</isbn><isbn>1479904945</isbn><eisbn>9781479904938</eisbn><eisbn>1479904937</eisbn><abstract>Motivated by the proposed NASA HyspIRI mission, our work improves existing Radiation Hardening by Software (RHBSW) techniques with FPGA Fabric Checkpoint/Restart (F2CPR) to bring enhanced hardware/software co-designed fault tolerance to commercial FPGA devices. We evaluate our approach on Fast Lossless (FL) image compression prediction for hyperspectral imagery in order to meet real-time performance requirements that cannot be achieved with aging radiation hardened devices. We report results across several metrics including resource utilization, performance, and an analysis of the vulnerability to Single Event Upsets (SEU) through the use of a hardware based fault injector. Results show low performance overhead (4-8%) achieving a speedup of 11.28× with a hardware accelerated implementation.</abstract><pub>IEEE</pub><doi>10.1109/ASAP.2013.6567560</doi><tpages>4</tpages></addata></record> |
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ispartof | 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, 2013, p.103-106 |
issn | 1063-6862 |
language | eng |
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source | IEEE Xplore All Conference Series |
subjects | Fabrics Fault tolerance Fault tolerant systems Field programmable gate arrays Hardware Radiation hardening (electronics) Software |
title | Fast lossless image compression with Radiation Hardening by hardware/software co-design on platform FPGAs |
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