A structured DC analysis methodology for accurate verification of analog circuits

This paper presents a structured DC analysis methodology for analog circuit verification. The electrical simulator, usually executed to perform verification, is here replaced by a nonlinear DC solver based on the analysis bipartite graph. The analysis bipartite graph, associated to a circuit, is a f...

Full description

Saved in:
Bibliographic Details
Main Authors: Javid, Farakh, Iskander, Ramy, Louerat, Marie-Minerve, Durbin, Francois
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Analog circuits
analog simulation
Analog sizing
Analytical models
Bipartite graph
bipartite graphs
Equations
fixed point iteration
Mathematical model
Transistors
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper presents a structured DC analysis methodology for analog circuit verification. The electrical simulator, usually executed to perform verification, is here replaced by a nonlinear DC solver based on the analysis bipartite graph. The analysis bipartite graph, associated to a circuit, is a formal representation of the circuit DC behavior. Thus, the analysis bipartite graph evaluation provides transistors currents and internal nodes voltages to meet the Kirchhoff's laws in the circuit. Currents and voltages are computed by dedicated operators using the fixed point iteration algorithm. Computed results accuracy is guaranteed by the standard transistor models used within the operators. The proposed verification methodology is efficiently applied on a folded cascode amplifier with several technologies.
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2013.6572426