3D Integration of CMOS image sensor with coprocessor using TSV last and micro-bumps technologies

This paper presents the prototype of a 3D circuit in which a Wafer Level Packaged CMOS image sensor is vertically assembled with an image signal processor in a face-to-back integration scheme. The design flow used to hybrydize the two circuits will be fully described, up to physical implementation....

Full description

Saved in:
Bibliographic Details
Main Authors: Coudrain, P., Henry, D., Berthelot, A., Charbonnier, J., Verrun, S., Franiatte, R., Bouzaida, N., Cibrario, G., Calmon, F., O'Connor, I., Lacrevaz, T., Fourneaud, L., Flechet, B., Chevrier, N., Farcy, A., Le-Briz, O.
Format: Conference Proceeding
Language:English
Subjects:
Coprocessors
Image sensors
Lithography
Passivation
Prototypes
Silicon
Through-silicon vias
Citations: Items that cite this one
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper presents the prototype of a 3D circuit in which a Wafer Level Packaged CMOS image sensor is vertically assembled with an image signal processor in a face-to-back integration scheme. The design flow used to hybrydize the two circuits will be fully described, up to physical implementation. The process technology carried out will be presented in a 200 mm environment. Finally, the 3D assembly will be successfully assessed, concretising the realism of a 3D technology for nomadic imaging systems.
ISSN:0569-5503
2377-5726
DOI:10.1109/ECTC.2013.6575646