Development of a Low CTE chip scale package

• Main Authors: Yamada, Tomoyuki, Fukui, Masahiro, Terada, Kenji, Harazono, Masaaki, Reynolds, Charles, Audet, Jean, Iruvanti, Sushumna, Hsichang Liu, Moore, Scott, Yi Pan, Hongqing Zhang
• Format: Conference Proceeding
• Language: English
• Subjects: Assembly; Chip scale packaging; Flip-chip devices; Laminates; Semiconductor device measurement; Temperature measurement
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2013.6575688

This paper describes the development of a low CTE organic Chip Scale Package (CSP) jointly by KST and IBM. Tests carried out on the low CTE laminate material and subsequently on the related CSP are described. The new material set, identified as Advanced SLC Package, combines low CTE core and build-up dielectric materials to achieve a composite laminate CTE of 9-12 ppm/°C, which is intermediate between the CTEs of silicon device and conventional board. The lower composite CTE reduces the dimensional mismatch between chip and laminate during Bond and Assembly (BA) to mitigate Chip-Package Interactions (CPI) and white bumps. The low CTE significantly reduces the strain in the solder joints during the reflow process and ensures the solder joint reliability. Global and chip-site warp data from thermo-mechanical modeling are compared to the measured warp data. In addition, other mechanical risk factors for a CSP during BA and reliability stress conditions are evaluated.