Innovative through-Si 3D lithography for ultimate self-aligned planar Double-Gate and Gate-All-Around nanowire transistors

This paper reports the first electrical results of self-aligned multigate devices based on an innovative 3D-lithography process. HSQ resist exposition through the Silicon channel allows the formation of self-aligned trenches in a single step. Planar Double-Gate (DG) and Gate-All-Around Silicon Nanow...

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Bibliographic Details
Main Authors: Coquand, R., Monfray, S., Barraud, S., Samson, M. P., Arvet, C., Pradelles, J., Bustos, J., Martin, L., Tosti, L., Perreau, P., Hartmann, J. M., Lacord, J., Casse, M., Clement, L., Pofelski, A., Lepinay, K., Ghibaudo, G., Faynot, O., Poiroux, T., Boeuf, F., Skotnicki, T., De Salvo, B.
Format: Conference Proceeding
Language:English
Subjects:
Lithography
Logic gates
Performance evaluation
Silicon
Silicon compounds
Silicon germanium
Very large scale integration
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Summary:This paper reports the first electrical results of self-aligned multigate devices based on an innovative 3D-lithography process. HSQ resist exposition through the Silicon channel allows the formation of self-aligned trenches in a single step. Planar Double-Gate (DG) and Gate-All-Around Silicon Nanowire (GAA Si NW) transistors are fabricated with conformal SiO 2 /Poly-Si:P gate stack and the first electrical results obtained with this technique are presented. The good nMOS performances (I ON =1mA/μm at V G =V T +0.7V) with excellent electrostatics (SS down to 62mV/dec and DIBL below 10mV/V at L G =80nm) are paving the way to the ultimate CMOS architecture. To meet all requirements of low-power SoCs, we also demonstrate the feasibility of fabricating such devices with High-K Metal-Gate (HK-MG) stack and their possible co-integration with FDSOI structures.
ISSN:0743-1562