A 64-fJ/Conv.-Step Continuous-Time \Sigma \Delta Modulator in 40-nm CMOS Using Asynchronous SAR Quantizer and Digital \Delta \Sigma Truncator

• Published in: IEEE journal of solid-state circuits 2013-11, Vol.48 (11), p.2637-2648
• Main Authors: Tsai, Hung-Chieh, Lo, Chi-Lun, Ho, Chen-Yen, Lin, Yu-Hsin
• Format: Article
• Language: English
• Subjects: AC-coupled push-pull; asynchronous successive approximation register (ASAR); continuous-time sigma-delta modulator (CTSDM); Delays; digital Delta \Sigma truncator; dynamic element matching (DEM); EDGE; Frequency modulation; GSM; low sampling frequency; Multiaccess communication; Noise; Spread spectrum communication; WCDMA
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2013.2274852

A third-order single-loop continuous-time sigma-delta modulator (CTSDM) with 6-bit asynchronous successive approximation register (ASAR) quantizer and digital ΔΣ truncator for WCDMA/GSM/EDGE cellular systems is presented. The proposed ASAR-based quantizer reduces the area and power of the modulator dramatically by utilizing the digital truncation technique. By using the 6-bit ASAR quantizer, the sampling frequency is lowered, which reduces the design efforts not only in system level but also in the modulator. In addition, the ac-coupled push-pull stage is employed to improve the high-frequency driving capability of the first integrator. Sampling at 65 MHz, the modulator achieves 83.4 dB dynamic range (DR) and 80/79.6 dB peak SNR/SNDR with 1.92 MHz bandwidth in WCDMA mode. In GSM/EDGE mode, the DR is 96.2 dB. Fabricated in 40-nm CMOS, the modulator occupies 0.051 mm 2 and consumes 1.91 mW from a 1.2-V supply. A 64fJ/conv.-step figure of merit is achieved.