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A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin
For the first time, 10nm Si-based bulk FinFETs 6T SRAM (beta ratio = 2) with novel multiple fin heights technology is successfully demonstrated with 25% better static noise margin at 0.6 V than single fin-height baseline. Meanwhile, presented technology also provides advantage in SRAM cell size by 2...
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| creator | Min-Cheng Chen Chang-Hsien Lin Yun-Fang Hou Yi-Ju Chen Chia-Yi Lin Fu-Kuo Hsueh Hsin-Liang Liu Cheng-Tsai Liu Bo-Wei Wang Hsiu-Chih Chen Chun-Chi Chen Shih-Hung Chen Chien-Ting Wu Tung-Yen Lai Mei-Yi Lee Bo-Wei Wu Cheng-San Wu Yang, Ivy Yi-Ping Hsieh ChiaHua Ho Tahui Wang Sachid, Angada B. Chenming Hu Fu-Liang Yang |
| description | For the first time, 10nm Si-based bulk FinFETs 6T SRAM (beta ratio = 2) with novel multiple fin heights technology is successfully demonstrated with 25% better static noise margin at 0.6 V than single fin-height baseline. Meanwhile, presented technology also provides advantage in SRAM cell size by 20% scaling down. It can furthermore offer potential of beyond 10nm Si-based CMOS computing circuit technology. |
| format | conference_proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6578756</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6578756</ieee_id><sourcerecordid>6578756</sourcerecordid><originalsourceid>FETCH-ieee_primary_65787563</originalsourceid><addsrcrecordid>eNp9jzFvwjAUhE0BqUD5BV1u6RjJxrGTjggVdelS2FECL8mjjoNiI8S_J0PVsdJJN3yfdLqRmKe51Wk-RD2J2UqZPDFW27GYq9Rm2hit9OQPSPUsliGcpZRKyUy-y5lo11ASvsWOk7IIdEJ5dT_Yst9-7APsHrvv9RduHBu0Vxf54ggVezTEdRMDIh0b37muvqPqeqzMG0qKkXqEWEQ-wnccCG3R1-xfxLQqXKDlby_E6zCz-UyYiA6XngftfrAmy7Phx__0AfExRv0</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Min-Cheng Chen ; Chang-Hsien Lin ; Yun-Fang Hou ; Yi-Ju Chen ; Chia-Yi Lin ; Fu-Kuo Hsueh ; Hsin-Liang Liu ; Cheng-Tsai Liu ; Bo-Wei Wang ; Hsiu-Chih Chen ; Chun-Chi Chen ; Shih-Hung Chen ; Chien-Ting Wu ; Tung-Yen Lai ; Mei-Yi Lee ; Bo-Wei Wu ; Cheng-San Wu ; Yang, Ivy ; Yi-Ping Hsieh ; ChiaHua Ho ; Tahui Wang ; Sachid, Angada B. ; Chenming Hu ; Fu-Liang Yang</creator><creatorcontrib>Min-Cheng Chen ; Chang-Hsien Lin ; Yun-Fang Hou ; Yi-Ju Chen ; Chia-Yi Lin ; Fu-Kuo Hsueh ; Hsin-Liang Liu ; Cheng-Tsai Liu ; Bo-Wei Wang ; Hsiu-Chih Chen ; Chun-Chi Chen ; Shih-Hung Chen ; Chien-Ting Wu ; Tung-Yen Lai ; Mei-Yi Lee ; Bo-Wei Wu ; Cheng-San Wu ; Yang, Ivy ; Yi-Ping Hsieh ; ChiaHua Ho ; Tahui Wang ; Sachid, Angada B. ; Chenming Hu ; Fu-Liang Yang</creatorcontrib><description>For the first time, 10nm Si-based bulk FinFETs 6T SRAM (beta ratio = 2) with novel multiple fin heights technology is successfully demonstrated with 25% better static noise margin at 0.6 V than single fin-height baseline. Meanwhile, presented technology also provides advantage in SRAM cell size by 20% scaling down. It can furthermore offer potential of beyond 10nm Si-based CMOS computing circuit technology.</description><identifier>ISSN: 2158-5601</identifier><identifier>ISBN: 1467355313</identifier><identifier>ISBN: 9781467355315</identifier><identifier>EISSN: 2158-5636</identifier><identifier>EISBN: 4863483481</identifier><identifier>EISBN: 9784863483484</identifier><language>eng</language><publisher>IEEE</publisher><subject>FinFETs ; Logic gates ; Noise ; Silicon ; SRAM cells ; Very large scale integration</subject><ispartof>2013 Symposium on VLSI Circuits, 2013, p.T218-T219</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6578756$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,54555,54920,54932</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6578756$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Min-Cheng Chen</creatorcontrib><creatorcontrib>Chang-Hsien Lin</creatorcontrib><creatorcontrib>Yun-Fang Hou</creatorcontrib><creatorcontrib>Yi-Ju Chen</creatorcontrib><creatorcontrib>Chia-Yi Lin</creatorcontrib><creatorcontrib>Fu-Kuo Hsueh</creatorcontrib><creatorcontrib>Hsin-Liang Liu</creatorcontrib><creatorcontrib>Cheng-Tsai Liu</creatorcontrib><creatorcontrib>Bo-Wei Wang</creatorcontrib><creatorcontrib>Hsiu-Chih Chen</creatorcontrib><creatorcontrib>Chun-Chi Chen</creatorcontrib><creatorcontrib>Shih-Hung Chen</creatorcontrib><creatorcontrib>Chien-Ting Wu</creatorcontrib><creatorcontrib>Tung-Yen Lai</creatorcontrib><creatorcontrib>Mei-Yi Lee</creatorcontrib><creatorcontrib>Bo-Wei Wu</creatorcontrib><creatorcontrib>Cheng-San Wu</creatorcontrib><creatorcontrib>Yang, Ivy</creatorcontrib><creatorcontrib>Yi-Ping Hsieh</creatorcontrib><creatorcontrib>ChiaHua Ho</creatorcontrib><creatorcontrib>Tahui Wang</creatorcontrib><creatorcontrib>Sachid, Angada B.</creatorcontrib><creatorcontrib>Chenming Hu</creatorcontrib><creatorcontrib>Fu-Liang Yang</creatorcontrib><title>A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin</title><title>2013 Symposium on VLSI Circuits</title><addtitle>VLSIC</addtitle><description>For the first time, 10nm Si-based bulk FinFETs 6T SRAM (beta ratio = 2) with novel multiple fin heights technology is successfully demonstrated with 25% better static noise margin at 0.6 V than single fin-height baseline. Meanwhile, presented technology also provides advantage in SRAM cell size by 20% scaling down. It can furthermore offer potential of beyond 10nm Si-based CMOS computing circuit technology.</description><subject>FinFETs</subject><subject>Logic gates</subject><subject>Noise</subject><subject>Silicon</subject><subject>SRAM cells</subject><subject>Very large scale integration</subject><issn>2158-5601</issn><issn>2158-5636</issn><isbn>1467355313</isbn><isbn>9781467355315</isbn><isbn>4863483481</isbn><isbn>9784863483484</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNp9jzFvwjAUhE0BqUD5BV1u6RjJxrGTjggVdelS2FECL8mjjoNiI8S_J0PVsdJJN3yfdLqRmKe51Wk-RD2J2UqZPDFW27GYq9Rm2hit9OQPSPUsliGcpZRKyUy-y5lo11ASvsWOk7IIdEJ5dT_Yst9-7APsHrvv9RduHBu0Vxf54ggVezTEdRMDIh0b37muvqPqeqzMG0qKkXqEWEQ-wnccCG3R1-xfxLQqXKDlby_E6zCz-UyYiA6XngftfrAmy7Phx__0AfExRv0</recordid><startdate>201306</startdate><enddate>201306</enddate><creator>Min-Cheng Chen</creator><creator>Chang-Hsien Lin</creator><creator>Yun-Fang Hou</creator><creator>Yi-Ju Chen</creator><creator>Chia-Yi Lin</creator><creator>Fu-Kuo Hsueh</creator><creator>Hsin-Liang Liu</creator><creator>Cheng-Tsai Liu</creator><creator>Bo-Wei Wang</creator><creator>Hsiu-Chih Chen</creator><creator>Chun-Chi Chen</creator><creator>Shih-Hung Chen</creator><creator>Chien-Ting Wu</creator><creator>Tung-Yen Lai</creator><creator>Mei-Yi Lee</creator><creator>Bo-Wei Wu</creator><creator>Cheng-San Wu</creator><creator>Yang, Ivy</creator><creator>Yi-Ping Hsieh</creator><creator>ChiaHua Ho</creator><creator>Tahui Wang</creator><creator>Sachid, Angada B.</creator><creator>Chenming Hu</creator><creator>Fu-Liang Yang</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201306</creationdate><title>A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin</title><author>Min-Cheng Chen ; Chang-Hsien Lin ; Yun-Fang Hou ; Yi-Ju Chen ; Chia-Yi Lin ; Fu-Kuo Hsueh ; Hsin-Liang Liu ; Cheng-Tsai Liu ; Bo-Wei Wang ; Hsiu-Chih Chen ; Chun-Chi Chen ; Shih-Hung Chen ; Chien-Ting Wu ; Tung-Yen Lai ; Mei-Yi Lee ; Bo-Wei Wu ; Cheng-San Wu ; Yang, Ivy ; Yi-Ping Hsieh ; ChiaHua Ho ; Tahui Wang ; Sachid, Angada B. ; Chenming Hu ; Fu-Liang Yang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_65787563</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>FinFETs</topic><topic>Logic gates</topic><topic>Noise</topic><topic>Silicon</topic><topic>SRAM cells</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Min-Cheng Chen</creatorcontrib><creatorcontrib>Chang-Hsien Lin</creatorcontrib><creatorcontrib>Yun-Fang Hou</creatorcontrib><creatorcontrib>Yi-Ju Chen</creatorcontrib><creatorcontrib>Chia-Yi Lin</creatorcontrib><creatorcontrib>Fu-Kuo Hsueh</creatorcontrib><creatorcontrib>Hsin-Liang Liu</creatorcontrib><creatorcontrib>Cheng-Tsai Liu</creatorcontrib><creatorcontrib>Bo-Wei Wang</creatorcontrib><creatorcontrib>Hsiu-Chih Chen</creatorcontrib><creatorcontrib>Chun-Chi Chen</creatorcontrib><creatorcontrib>Shih-Hung Chen</creatorcontrib><creatorcontrib>Chien-Ting Wu</creatorcontrib><creatorcontrib>Tung-Yen Lai</creatorcontrib><creatorcontrib>Mei-Yi Lee</creatorcontrib><creatorcontrib>Bo-Wei Wu</creatorcontrib><creatorcontrib>Cheng-San Wu</creatorcontrib><creatorcontrib>Yang, Ivy</creatorcontrib><creatorcontrib>Yi-Ping Hsieh</creatorcontrib><creatorcontrib>ChiaHua Ho</creatorcontrib><creatorcontrib>Tahui Wang</creatorcontrib><creatorcontrib>Sachid, Angada B.</creatorcontrib><creatorcontrib>Chenming Hu</creatorcontrib><creatorcontrib>Fu-Liang Yang</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Min-Cheng Chen</au><au>Chang-Hsien Lin</au><au>Yun-Fang Hou</au><au>Yi-Ju Chen</au><au>Chia-Yi Lin</au><au>Fu-Kuo Hsueh</au><au>Hsin-Liang Liu</au><au>Cheng-Tsai Liu</au><au>Bo-Wei Wang</au><au>Hsiu-Chih Chen</au><au>Chun-Chi Chen</au><au>Shih-Hung Chen</au><au>Chien-Ting Wu</au><au>Tung-Yen Lai</au><au>Mei-Yi Lee</au><au>Bo-Wei Wu</au><au>Cheng-San Wu</au><au>Yang, Ivy</au><au>Yi-Ping Hsieh</au><au>ChiaHua Ho</au><au>Tahui Wang</au><au>Sachid, Angada B.</au><au>Chenming Hu</au><au>Fu-Liang Yang</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin</atitle><btitle>2013 Symposium on VLSI Circuits</btitle><stitle>VLSIC</stitle><date>2013-06</date><risdate>2013</risdate><spage>T218</spage><epage>T219</epage><pages>T218-T219</pages><issn>2158-5601</issn><eissn>2158-5636</eissn><isbn>1467355313</isbn><isbn>9781467355315</isbn><eisbn>4863483481</eisbn><eisbn>9784863483484</eisbn><abstract>For the first time, 10nm Si-based bulk FinFETs 6T SRAM (beta ratio = 2) with novel multiple fin heights technology is successfully demonstrated with 25% better static noise margin at 0.6 V than single fin-height baseline. Meanwhile, presented technology also provides advantage in SRAM cell size by 20% scaling down. It can furthermore offer potential of beyond 10nm Si-based CMOS computing circuit technology.</abstract><pub>IEEE</pub></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 2158-5601 |
| ispartof | 2013 Symposium on VLSI Circuits, 2013, p.T218-T219 |
| issn | 2158-5601 2158-5636 |
| language | eng |
| recordid | cdi_ieee_primary_6578756 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | FinFETs Logic gates Noise Silicon SRAM cells Very large scale integration |
| title | A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin |
| url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-06T17%3A26%3A41IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%2010%20nm%20Si-based%20bulk%20FinFETs%206T%20SRAM%20with%20multiple%20fin%20heights%20technology%20for%2025%25%20better%20static%20noise%20margin&rft.btitle=2013%20Symposium%20on%20VLSI%20Circuits&rft.au=Min-Cheng%20Chen&rft.date=2013-06&rft.spage=T218&rft.epage=T219&rft.pages=T218-T219&rft.issn=2158-5601&rft.eissn=2158-5636&rft.isbn=1467355313&rft.isbn_list=9781467355315&rft_id=info:doi/&rft.eisbn=4863483481&rft.eisbn_list=9784863483484&rft_dat=%3Cieee_6IE%3E6578756%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-ieee_primary_65787563%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6578756&rfr_iscdi=true |