Reliability test chips: NIST 33 and NIST 34 for JEDEC inter-laboratory experiments and more

Two reliability test patterns, NIST 33 and NIST 34, are being designed, and a third, NIST 36, is being planned to be used in a number of inter-laboratory experiments as part of the activities of the Metal Reliability Task Group of the EIA/JEDEC Committee JC 14.2 on Wafer Level Reliability. These chi...

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Bibliographic Details
Main Author: Schafft, H.A.
Format: Conference Proceeding
Language:English
Subjects:
Electrical resistance measurement
Electromigration
Electronic equipment testing
Isothermal processes
NIST
Semiconductor device reliability
Stress measurement
Thermal conductivity
Thermal stresses
X-ray diffraction
Online Access:Request full text
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Summary:Two reliability test patterns, NIST 33 and NIST 34, are being designed, and a third, NIST 36, is being planned to be used in a number of inter-laboratory experiments as part of the activities of the Metal Reliability Task Group of the EIA/JEDEC Committee JC 14.2 on Wafer Level Reliability. These chips will also be used for other tasks, many of which will provide additional characterization data in support of the JEDEC inter-laboratory experiments.
DOI:10.1109/IRWS.1997.660312