Device design methodology and reliability strategy for deep sub-micron technology [DRAMs]

This tutorial paper discusses device and process optimization techniques that may be employed in the design of current state-of-the-art bulk silicon DRAM technology. MOSFET performance and reliability issues are contrasted.

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Bibliographic Details
Main Authors: Divakaruni, R., El-Kareh, B., Tonti, W.R.
Format: Conference Proceeding
Language:English
Subjects:
Boron
Degradation
Design methodology
Doping
High definition video
Hot carriers
Implants
MOSFET circuits
Random access memory
Threshold voltage
Online Access:Request full text
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Description
Summary:This tutorial paper discusses device and process optimization techniques that may be employed in the design of current state-of-the-art bulk silicon DRAM technology. MOSFET performance and reliability issues are contrasted.
DOI:10.1109/IRWS.1997.660315