An analog 1:16 demultiplexer for time-interleaved A/D-converters with a sampling rate of up to 64 GS/s

An analog current-based 1:16-demultiplexer with integrated sample-and-hold is presented. It is designed in a 28 nm CMOS technology and is the basis for a 16-fold time-interleaved ADC. It offers sampling rates up to 64 GS/s, while consuming only 0.9 W of power and 2.6 mm 2 of chip area.

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Bibliographic Details
Main Authors: Lang, Felix, Gerigk, Janina, Ferenci, Damir, Grozing, Markus, Berroth, Manfred
Format: Conference Proceeding
Language:English
Subjects:
Analog integrated circuits
Analog-digital conversion
Capacitors
Clocks
CMOS integrated circuits
Demultiplexing
Jitter
Signal sampling
Switches
Synchronization
Transistors
Online Access:Request full text
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Description
Summary:An analog current-based 1:16-demultiplexer with integrated sample-and-hold is presented. It is designed in a 28 nm CMOS technology and is the basis for a 16-fold time-interleaved ADC. It offers sampling rates up to 64 GS/s, while consuming only 0.9 W of power and 2.6 mm 2 of chip area.
DOI:10.1109/PRIME.2013.6603150