Hardware software co-design of pipelined instruction decoder in system emulation

System emulation based on dynamic binary translation can solve the problems of compatibility between heterogeneous architectures. Study on this field is mostly based on software, the efficiency is very low and restricting the performance of X86 system emulator. This paper presents hardware software...

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Bibliographic Details
Main Authors: Sichun Zhang, Liehui Jiang, Xiaojuan Zhang, Xiaolong Hu
Format: Conference Proceeding
Language:English
Subjects:
co-design
Decoding
Hardware
instruction decoder
length of instruction
pipelined stages
Prefetching
system emulation
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Summary:System emulation based on dynamic binary translation can solve the problems of compatibility between heterogeneous architectures. Study on this field is mostly based on software, the efficiency is very low and restricting the performance of X86 system emulator. This paper presents hardware software co-design of pipelined instruction decoder to avoid the inefficiency of system emulator based on software. The decoder is controlled by the software unit and supported by the hardware unit via cross-programing. Compared to system emulator based on software, the average speedup of pipelined instruction decoder achieves 5.2 and there is a significant performance improvement on system emulation.
ISSN:2327-0586
DOI:10.1109/ICSESS.2013.6615276