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On Monolayer Field-Effect Transistors at the Scaling Limit
The ultimate scaling limit of double-gate molybdenum disulfide (MoS 2 ) field-effect transistors (FETs) with a monolayer thin body is examined and compared with ultrathin-body Si FETs by self-consistent quantum transport simulation in the presence of phonon scattering. Modeling of phonon scattering,...
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Published in: | IEEE transactions on electron devices 2013-12, Vol.60 (12), p.4133-4139 |
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creator | Liu, Leitao Lu, Yang Guo, Jing |
description | The ultimate scaling limit of double-gate molybdenum disulfide (MoS 2 ) field-effect transistors (FETs) with a monolayer thin body is examined and compared with ultrathin-body Si FETs by self-consistent quantum transport simulation in the presence of phonon scattering. Modeling of phonon scattering, quantum mechanical effects, and self-consistent electrostatics allows us to accurately assess the performance potential of monolayer MoS 2 FETs. The results revealed that monolayer MoS 2 FETs show 52% smaller drain-induced barrier lowering (DIBL) and 13% smaller subthreshold swing (SS) than 3-nm-thick-body Si FETs at a channel length of 10 nm with the same gating. With a requirement of DIBL , the scaling limit of monolayer MoS 2 FETs is assessed to be 8 nm, comparing with 10 nm of the ultrathin-body Si counterparts due to the monolayer thin body and higher effective mass, which reduces direct source-to-drain tunneling. By comparing with the international technology roadmap for semiconductor (ITRS) target for high performance logic devices of 2023; double-gate monolayer MoS 2 FETs can fulfill the ITRS requirements. |
doi_str_mv | 10.1109/TED.2013.2284591 |
format | article |
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Modeling of phonon scattering, quantum mechanical effects, and self-consistent electrostatics allows us to accurately assess the performance potential of monolayer MoS 2 FETs. The results revealed that monolayer MoS 2 FETs show 52% smaller drain-induced barrier lowering (DIBL) and 13% smaller subthreshold swing (SS) than 3-nm-thick-body Si FETs at a channel length of 10 nm with the same gating. With a requirement of DIBL , the scaling limit of monolayer MoS 2 FETs is assessed to be 8 nm, comparing with 10 nm of the ultrathin-body Si counterparts due to the monolayer thin body and higher effective mass, which reduces direct source-to-drain tunneling. By comparing with the international technology roadmap for semiconductor (ITRS) target for high performance logic devices of 2023; double-gate monolayer MoS 2 FETs can fulfill the ITRS requirements.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2013.2284591</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>IEEE</publisher><subject>Double-gate field-effect transistors (FETs) ; Field effect transistors ; Logic gates ; monolayer molybdenum disulfide {\rm MoS}_{{2}} ; performance metrics ; phonon scattering ; Phonons ; Scattering ; Silicon ; Tunneling ; ultimate scaling limit</subject><ispartof>IEEE transactions on electron devices, 2013-12, Vol.60 (12), p.4133-4139</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c1740-fedfd0f52fcf0b049bcdca22a6b1b5c0bce7971c0179d2250517ea49eb8a74e13</citedby><cites>FETCH-LOGICAL-c1740-fedfd0f52fcf0b049bcdca22a6b1b5c0bce7971c0179d2250517ea49eb8a74e13</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6636047$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,54796</link.rule.ids></links><search><creatorcontrib>Liu, Leitao</creatorcontrib><creatorcontrib>Lu, Yang</creatorcontrib><creatorcontrib>Guo, Jing</creatorcontrib><title>On Monolayer Field-Effect Transistors at the Scaling Limit</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>The ultimate scaling limit of double-gate molybdenum disulfide (MoS 2 ) field-effect transistors (FETs) with a monolayer thin body is examined and compared with ultrathin-body Si FETs by self-consistent quantum transport simulation in the presence of phonon scattering. Modeling of phonon scattering, quantum mechanical effects, and self-consistent electrostatics allows us to accurately assess the performance potential of monolayer MoS 2 FETs. The results revealed that monolayer MoS 2 FETs show 52% smaller drain-induced barrier lowering (DIBL) and 13% smaller subthreshold swing (SS) than 3-nm-thick-body Si FETs at a channel length of 10 nm with the same gating. With a requirement of DIBL , the scaling limit of monolayer MoS 2 FETs is assessed to be 8 nm, comparing with 10 nm of the ultrathin-body Si counterparts due to the monolayer thin body and higher effective mass, which reduces direct source-to-drain tunneling. By comparing with the international technology roadmap for semiconductor (ITRS) target for high performance logic devices of 2023; double-gate monolayer MoS 2 FETs can fulfill the ITRS requirements.</description><subject>Double-gate field-effect transistors (FETs)</subject><subject>Field effect transistors</subject><subject>Logic gates</subject><subject>monolayer molybdenum disulfide {\rm MoS}_{{2}}</subject><subject>performance metrics</subject><subject>phonon scattering</subject><subject>Phonons</subject><subject>Scattering</subject><subject>Silicon</subject><subject>Tunneling</subject><subject>ultimate scaling limit</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><recordid>eNo9j01LAzEURYMoWKt7wU3-wNT3MvmYuJPaVqHShXU9ZDIvGpnOSDKb_ntbWlxdLtxz4TB2jzBDBPu4XbzMBGA5E6KSyuIFm6BSprBa6ks2AcCqsGVVXrObnH8OVUspJuxp0_P3oR86t6fEl5G6tliEQH7k2-T6HPM4pMzdyMdv4h_edbH_4uu4i-Mtuwquy3R3zin7XC6289divVm9zZ_XhUcjoQjUhhaCEsEHaEDaxrfeCeF0g43y0Hgy1qAHNLYVQoFCQ05aaipnJGE5ZXD69WnIOVGof1PcubSvEeqje31wr4_u9dn9gDyckEhE_3OtSw3SlH8h71Uc</recordid><startdate>201312</startdate><enddate>201312</enddate><creator>Liu, Leitao</creator><creator>Lu, Yang</creator><creator>Guo, Jing</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>201312</creationdate><title>On Monolayer Field-Effect Transistors at the Scaling Limit</title><author>Liu, Leitao ; Lu, Yang ; Guo, Jing</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c1740-fedfd0f52fcf0b049bcdca22a6b1b5c0bce7971c0179d2250517ea49eb8a74e13</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Double-gate field-effect transistors (FETs)</topic><topic>Field effect transistors</topic><topic>Logic gates</topic><topic>monolayer molybdenum disulfide {\rm MoS}_{{2}}</topic><topic>performance metrics</topic><topic>phonon scattering</topic><topic>Phonons</topic><topic>Scattering</topic><topic>Silicon</topic><topic>Tunneling</topic><topic>ultimate scaling limit</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Liu, Leitao</creatorcontrib><creatorcontrib>Lu, Yang</creatorcontrib><creatorcontrib>Guo, Jing</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore (Online service)</collection><collection>CrossRef</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Liu, Leitao</au><au>Lu, Yang</au><au>Guo, Jing</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>On Monolayer Field-Effect Transistors at the Scaling Limit</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2013-12</date><risdate>2013</risdate><volume>60</volume><issue>12</issue><spage>4133</spage><epage>4139</epage><pages>4133-4139</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>The ultimate scaling limit of double-gate molybdenum disulfide (MoS 2 ) field-effect transistors (FETs) with a monolayer thin body is examined and compared with ultrathin-body Si FETs by self-consistent quantum transport simulation in the presence of phonon scattering. Modeling of phonon scattering, quantum mechanical effects, and self-consistent electrostatics allows us to accurately assess the performance potential of monolayer MoS 2 FETs. The results revealed that monolayer MoS 2 FETs show 52% smaller drain-induced barrier lowering (DIBL) and 13% smaller subthreshold swing (SS) than 3-nm-thick-body Si FETs at a channel length of 10 nm with the same gating. With a requirement of DIBL , the scaling limit of monolayer MoS 2 FETs is assessed to be 8 nm, comparing with 10 nm of the ultrathin-body Si counterparts due to the monolayer thin body and higher effective mass, which reduces direct source-to-drain tunneling. By comparing with the international technology roadmap for semiconductor (ITRS) target for high performance logic devices of 2023; double-gate monolayer MoS 2 FETs can fulfill the ITRS requirements.</abstract><pub>IEEE</pub><doi>10.1109/TED.2013.2284591</doi><tpages>7</tpages></addata></record> |
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subjects | Double-gate field-effect transistors (FETs) Field effect transistors Logic gates monolayer molybdenum disulfide {\rm MoS}_{{2}} performance metrics phonon scattering Phonons Scattering Silicon Tunneling ultimate scaling limit |
title | On Monolayer Field-Effect Transistors at the Scaling Limit |
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