If SystemVerilog is so good, why do we need the UVM? Sharing responsibilities between libraries and the core language

Probably the most effective catalyst for widespread adoption of advanced SystemVerilog features has been availability of the Universal Verification Methodology (UVM). In addition to a rich base class library, it provides a reference best-practice verification methodology. Fully supported by major to...

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Bibliographic Details
Main Author: Bromley, Jonathan
Format: Conference Proceeding
Language:English
Subjects:
Design Verification
Hardware design languages
Libraries
Manuals
Production facilities
Protocols
SystemVerilog
Universal Verification Methodology
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Summary:Probably the most effective catalyst for widespread adoption of advanced SystemVerilog features has been availability of the Universal Verification Methodology (UVM). In addition to a rich base class library, it provides a reference best-practice verification methodology. Fully supported by major tool vendors, and maintained by an industry-recognized body (Accellera) UVM has enjoyed widespread adoption by a diverse user base. For many users, "verification using SystemVerilog" is synonymous with "verification using the UVM". After outlining the UVM's value to users, and discussing how it has built on field-proven techniques from other languages and methodologies, this paper goes on to explore the relationship between the UVM and its host language SystemVerilog. In particular, it considers whether the addition of some features to SystemVerilog could have made the UVM smaller, easier to use, or even completely redundant. After examining some selected technical challenges and their solutions, the paper concludes that the needs of users are best served by a combination of an expressive base language and a comprehensive reference methodology.
ISSN:1636-9874