High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line

In this paper, we propose a time-to-digital converter (TDC) that uses a multi-phase cyclic Vernier delay line (VDL) to achieve the high-resolution and wide-dynamic range. Its control voltages are provided by two phase-locked loops (PLLs) to compensate for the process and ambient variations. The two...

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Bibliographic Details
Main Authors: Mino Kim, Woo-Yeol Shin, Gi-Moon Hong, Jihwan Park, Joo-Hyung Chae, Nan Xing, Jong-Kwan Woo, Suhwan Kim
Format: Conference Proceeding
Language:English
Subjects:
Clocks
CMOS integrated circuits
Delay lines
Delays
Dynamic range
Phase locked loops
Radiation detectors
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Summary:In this paper, we propose a time-to-digital converter (TDC) that uses a multi-phase cyclic Vernier delay line (VDL) to achieve the high-resolution and wide-dynamic range. Its control voltages are provided by two phase-locked loops (PLLs) to compensate for the process and ambient variations. The two PLLs share a single reference clock and have different frequency-division ratios. It also improves the resolution of the TDC. A prototype chip, designed and fabricated in 0.18μm CMOS technology with an active area of 0.40mm 2 , achieves a 3.4ps of resolution and an input range of 100ns at 2.5M samples/s, while consuming 32mW from a 1.8V supply.
ISSN:1930-8833
2643-1319
DOI:10.1109/ESSCIRC.2013.6649135