An area-efficient BCH codec with echelon scheduling for NAND flash applications

This paper presents an area-efficient BCH codec with echelon scheduling for NAND flash memory systems. In our proposed design, instead of the common inversionless Berlekamp-Massey algorithm, the BM algorithm using a low-complexity 2-stage composite field divider is applied in the key equation solver...

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Bibliographic Details
Main Authors: Chi-Heng Yang, Yi-Hsun Chen, Hsie-Chia Chang
Format: Conference Proceeding
Language:English
Subjects:
Calculators
Clocks
Codecs
Computer architecture
Mathematical model
Polynomials
Online Access:Request full text
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Summary:This paper presents an area-efficient BCH codec with echelon scheduling for NAND flash memory systems. In our proposed design, instead of the common inversionless Berlekamp-Massey algorithm, the BM algorithm using a low-complexity 2-stage composite field divider is applied in the key equation solver. Moreover, by making use of the fact that the degree of error locator polynomial increases at most by 1 in each iteration, an echelon scheduling architecture with 6 finite field multipliers is presented. After implemented in UMC 1P9M 90 nm process, the proposed codec can achieve 385 MHz and 3.08 Gbit/s throughput with 147.8K gate-count from post-layout simulation results.
ISSN:1550-3607
1938-1883
DOI:10.1109/ICC.2013.6655246