A PVT insensitive field programmable gate array time-to-digital converter

A process, voltage and temperature (PVT) insensitive time-to-digital converter (TDC) implemented in field programmable gate array (FPGA) is presented. The aim is to provide a PVT insensitive TDC solution with god enough resolution and wide measurement range. With the aid of FPGA embedded phase locke...

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Bibliographic Details
Main Authors: Poki Chen, Hsiu Che Cheng, Widodo, Arif, Wei Xiang Tsai
Format: Conference Proceeding
Language:English
Subjects:
Clocks
field programmable gate array (FPGA
Field programmable gate arrays
Image resolution
Measurement uncertainty
Phase locked loops
phase-locked loop (PLL)
PVT insensitivity
Temperature measurement
time-to-digital converter
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Summary:A process, voltage and temperature (PVT) insensitive time-to-digital converter (TDC) implemented in field programmable gate array (FPGA) is presented. The aim is to provide a PVT insensitive TDC solution with god enough resolution and wide measurement range. With the aid of FPGA embedded phase locked loop (PLL) which provides eight different output phases, a constant resolution around 84 ps can be ensured. The short term differential nonlinearity (DNL) is measured to be -0.482 ~ 0.457 LSB, and the corresponding integral nonlinearity (INL) is merely -0.612 ~ 0.575 LSB. This TDC was tested to be fully functional over 0°C to 50°C ambient temperature ranges with extremely low variation on resolution.
DOI:10.1109/NoMeTDC.2013.6658232