A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation

We describe the implementation and silicon measurement results from a Razor-based hardware loop-accelerator (RZLA), implementing the Sobel edge-detection algorithm. We demonstrate robust operation with a large Dynamic Voltage Scaling (DVS) range achieved using 50% of the clock-period for timing-spec...

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Bibliographic Details
Main Authors: Das, Shidhartha, Dasika, Ganesh, Shivashankar, Karthik, Bull, David
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Energy efficiency
Hardware
Latches
Microprocessors
Timing
Voltage control
Online Access:Request full text
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Summary:We describe the implementation and silicon measurement results from a Razor-based hardware loop-accelerator (RZLA), implementing the Sobel edge-detection algorithm. We demonstrate robust operation with a large Dynamic Voltage Scaling (DVS) range achieved using 50% of the clock-period for timing-speculation. At 1GHz operating frequency, Razor DVS enables 34% energy-efficiency improvement on a per-device basis and 33% overall on the entire batch of devices.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2013.6658432