Modified integrated circuit interface based on M×N-ary variable width period modulation

A modified IC interface based on M×N-ary variable width period modulation is proposed to reduce the complexity of circuit design, and to improve the data transfer rate of a bandwidth-limited system. A demonstration system is built by using two Field Programmable Gate Arrays to simulate the transceiv...

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Bibliographic Details
Main Authors: Shengyang He, Maoliu Lin, Guanghui Ren
Format: Conference Proceeding
Language:English
Subjects:
Bandwidth
Clocks
Complexity theory
Data transfer
Demodulation
Integrated circuits
Online Access:Request full text
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Description
Summary:A modified IC interface based on M×N-ary variable width period modulation is proposed to reduce the complexity of circuit design, and to improve the data transfer rate of a bandwidth-limited system. A demonstration system is built by using two Field Programmable Gate Arrays to simulate the transceiver functions in a RS232 bus, and to verify the feasibility and validity of the interface proposed. Theoretical analysis and experimental results indicates that, the interface proposed can be used not only to reduce the bandwidth and the switching frequency requirements, thereby reducing the design complexity of a high-speed system, but also to increase the data transfer rate of a bandwidth-limited system. Experimental results indicate that a data transfer rate of more than 1.1 Mbps can be achieved using the interface proposed in a RS232 serial bus without any other change in hardware circuit.
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2013.6674596