Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications

• Main Authors: Teng-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
• Format: Conference Proceeding
• Language: English
• Subjects: Arrays; Capacitance; Capacitors; Clocks; Indium phosphide; Sensors; Tuning
• ISSN: 2163-4025; 2766-4465
• DOI: 10.1109/BioCAS.2013.6679683

In this paper, an area-power-efficient 11-bit hybrid analog-to-digital converter (ADC) with delay-line enhanced tuning for neural sensing applications is presented. To reduce the total amount of capacitance, this hybrid ADC is composed of a coarse tune and a fine tune by 3-bit delay-lined-based ADC and 8-bit successive approximation register (SAR) ADC, respectively. The delay-lined-based ADC is designed to detect the three most significant bits by a modified vernier structure. To relax the accuracy requirement of the coarse tune, the lifting-based searching algorithm and re-comparison procedure are proposed for the fine tune. To further achieve energy saving, split capacitor array and self-timed control are utilized in the SAR ADC. Fabricated in TSMC 0.18μm CMOS technology, an ENOB of 10.4-bit at 8KS/s can be achieved with only 0.6μW power consumption and 0.032-mm 2 area. The FoM of this ADC is 49.4fJ/conversion-step.