Multi-histogram ADC BIST System for ADC Linearity Testing

This paper describes an ADC BIST system that utilizes a modified linear ramp histogram approach to test the linearity of an ADC with 10 bits of resolution on a System-On-Chip (SoC). The system tests the differential non-linearity (DNL) and Integral Non-linearity (INL) of an ADC. The ADC is tested in...

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Bibliographic Details
Main Authors: Koay Soon Chan, Nordin, Nuzrul Fahmi, Kim Chon Chan, Terk Zyou Lok, Chee Wai Yong
Format: Conference Proceeding
Language:English
Subjects:
ADC BIST
ADC linearity test
Built-in self-test
Capacitors
Histogram testing
Histograms
Linearity
Simulation
System-on-chip
Triangle wave
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Description
Summary:This paper describes an ADC BIST system that utilizes a modified linear ramp histogram approach to test the linearity of an ADC with 10 bits of resolution on a System-On-Chip (SoC). The system tests the differential non-linearity (DNL) and Integral Non-linearity (INL) of an ADC. The ADC is tested in sections using a small amplitude triangle wave which is generated by charging and discharging an on-chip capacitor. This is an alternative solution to test an ADC when ADC-DAC loopback testing is not feasible. Both the ADC and BIST are designed in the 40 nm process node. Simulation results show that the BIST is capable of testing a 10-bit ADC.
ISSN:1081-7735
2377-5386
DOI:10.1109/ATS.2013.47