A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit

This paper presents SRAM circuit techniques to reduce both active and standby mode power especially at room temperature (RT) where actual power consumption is dominant. A bit line power calculator is used to adaptively set the cell supply voltage (V CS ) in the active mode. A digitally controllable...

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Bibliographic Details
Main Authors: Kushida, Keiichi, Tachibana, Fumihiko, Hirabayashi, Osamu, Takeyama, Yasuhisa, Shizuno, Miyako, Kawasumi, Atsushi, Suzuki, Azuma, Niki, Yusuke, Sasaki, Shinichi, Yabe, Tomoaki, Unekawa, Yasuo
Format: Conference Proceeding
Language:English
Subjects:
Calculators
Leakage currents
Logic gates
Power demand
Random access memory
Temperature
Voltage control
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Summary:This paper presents SRAM circuit techniques to reduce both active and standby mode power especially at room temperature (RT) where actual power consumption is dominant. A bit line power calculator is used to adaptively set the cell supply voltage (V CS ) in the active mode. A digitally controllable retention circuit regulates V CS in the standby mode with small control power. These circuits are implemented in a dual-power-supply SRAM in 28 nm CMOS technology. Compared with the conventional scheme, the power consumption in the active and standby mode at 25°C is reduced by 27% and 85%, respectively.
DOI:10.1109/ASSCC.2013.6690973