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A 0.6-V input 94% peak efficiency CCM/DCM digital buck converter in 40-nm CMOS with dual-mode-body-biased zero-crossing detector

A 0.6-V input, 0.3-0.55V output buck converter is developed in 40-nm CMOS, for low-voltage low-power wireless sensor network systems. The buck converter is able to automatically select DCM or CCM operation, therefore improving the power efficiency and enlarging the output current range, by virtue of...

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Main Authors: Xin Zhang, Okuma, Yasuyuki, Po-Hung Chen, Ishida, Koichi, Ryu, Yoshikatsu, Watanabe, Kazumori, Sakurai, Takayasu, Takamiya, Makoto
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container_start_page 45
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creator Xin Zhang
Okuma, Yasuyuki
Po-Hung Chen
Ishida, Koichi
Ryu, Yoshikatsu
Watanabe, Kazumori
Sakurai, Takayasu
Takamiya, Makoto
description A 0.6-V input, 0.3-0.55V output buck converter is developed in 40-nm CMOS, for low-voltage low-power wireless sensor network systems. The buck converter is able to automatically select DCM or CCM operation, therefore improving the power efficiency and enlarging the output current range, by virtue of the proposed low-power CCM/DCM controller. A dual-mode-body-biased (DMBB) (forward body bias & zero body bias) low-voltage zero-crossing detector is designed to enable DCM operation with both low supply voltage and normal supply voltage. The proposed buck converter achieves a peak efficiency of 94% with an output current range of 50μA to 10mA. Thanks to the DCM operation, the efficiency at an output current of 100μA is improved by 20% and 9%, with an output voltage of 0.35V and 0.5V, respectively.
doi_str_mv 10.1109/ASSCC.2013.6690978
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fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6690978</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6690978</ieee_id><sourcerecordid>6690978</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-7151c4038dcdbf0eb223a1b8fabcb687942eac3edb3c13c58ef1a32f7eaf6d553</originalsourceid><addsrcrecordid>eNo9kDtPwzAUhY0QElD6B2C5C6NTP5I4GSvzlFp1KLBWflwX0zapnBRUJn46laiYjs7wHX06hFxzlnHO6tF4Ptc6E4zLrCxrVqvqhFzyXNU1ExUTp_9FKXFOhl33wRjjqigLyS_IzxhYVtI3iM1210Od38IWzQowhOgiNm4PWk9Hd3oKPi5jb9Zgd24Frm0-MfWYDiDkjDYb0NPZHL5i_w5-Z9Z003qktvV7aqPp0MM3ppa61HZdbJbgsUfXt-mKnAWz7nB4zAF5fbh_0U90Mnt81uMJjQfXnipecJczWXnnbWBohZCG2yoY62xZqToXaJxEb6Xj0hUVBm6kCApNKH1RyAG5-duNiLjYprgxab84PiZ_ARC7X00</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A 0.6-V input 94% peak efficiency CCM/DCM digital buck converter in 40-nm CMOS with dual-mode-body-biased zero-crossing detector</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Xin Zhang ; Okuma, Yasuyuki ; Po-Hung Chen ; Ishida, Koichi ; Ryu, Yoshikatsu ; Watanabe, Kazumori ; Sakurai, Takayasu ; Takamiya, Makoto</creator><creatorcontrib>Xin Zhang ; Okuma, Yasuyuki ; Po-Hung Chen ; Ishida, Koichi ; Ryu, Yoshikatsu ; Watanabe, Kazumori ; Sakurai, Takayasu ; Takamiya, Makoto</creatorcontrib><description>A 0.6-V input, 0.3-0.55V output buck converter is developed in 40-nm CMOS, for low-voltage low-power wireless sensor network systems. The buck converter is able to automatically select DCM or CCM operation, therefore improving the power efficiency and enlarging the output current range, by virtue of the proposed low-power CCM/DCM controller. A dual-mode-body-biased (DMBB) (forward body bias &amp; zero body bias) low-voltage zero-crossing detector is designed to enable DCM operation with both low supply voltage and normal supply voltage. The proposed buck converter achieves a peak efficiency of 94% with an output current range of 50μA to 10mA. Thanks to the DCM operation, the efficiency at an output current of 100μA is improved by 20% and 9%, with an output voltage of 0.35V and 0.5V, respectively.</description><identifier>ISBN: 1479902772</identifier><identifier>ISBN: 9781479902774</identifier><identifier>EISBN: 1479902802</identifier><identifier>EISBN: 9781479902804</identifier><identifier>DOI: 10.1109/ASSCC.2013.6690978</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; CMOS integrated circuits ; Detectors ; Inductors ; Logic gates ; Pulse width modulation ; Voltage control</subject><ispartof>2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2013, p.45-48</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6690978$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6690978$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Xin Zhang</creatorcontrib><creatorcontrib>Okuma, Yasuyuki</creatorcontrib><creatorcontrib>Po-Hung Chen</creatorcontrib><creatorcontrib>Ishida, Koichi</creatorcontrib><creatorcontrib>Ryu, Yoshikatsu</creatorcontrib><creatorcontrib>Watanabe, Kazumori</creatorcontrib><creatorcontrib>Sakurai, Takayasu</creatorcontrib><creatorcontrib>Takamiya, Makoto</creatorcontrib><title>A 0.6-V input 94% peak efficiency CCM/DCM digital buck converter in 40-nm CMOS with dual-mode-body-biased zero-crossing detector</title><title>2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)</title><addtitle>ASSCC</addtitle><description>A 0.6-V input, 0.3-0.55V output buck converter is developed in 40-nm CMOS, for low-voltage low-power wireless sensor network systems. The buck converter is able to automatically select DCM or CCM operation, therefore improving the power efficiency and enlarging the output current range, by virtue of the proposed low-power CCM/DCM controller. A dual-mode-body-biased (DMBB) (forward body bias &amp; zero body bias) low-voltage zero-crossing detector is designed to enable DCM operation with both low supply voltage and normal supply voltage. The proposed buck converter achieves a peak efficiency of 94% with an output current range of 50μA to 10mA. Thanks to the DCM operation, the efficiency at an output current of 100μA is improved by 20% and 9%, with an output voltage of 0.35V and 0.5V, respectively.</description><subject>Clocks</subject><subject>CMOS integrated circuits</subject><subject>Detectors</subject><subject>Inductors</subject><subject>Logic gates</subject><subject>Pulse width modulation</subject><subject>Voltage control</subject><isbn>1479902772</isbn><isbn>9781479902774</isbn><isbn>1479902802</isbn><isbn>9781479902804</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo9kDtPwzAUhY0QElD6B2C5C6NTP5I4GSvzlFp1KLBWflwX0zapnBRUJn46laiYjs7wHX06hFxzlnHO6tF4Ptc6E4zLrCxrVqvqhFzyXNU1ExUTp_9FKXFOhl33wRjjqigLyS_IzxhYVtI3iM1210Od38IWzQowhOgiNm4PWk9Hd3oKPi5jb9Zgd24Frm0-MfWYDiDkjDYb0NPZHL5i_w5-Z9Z003qktvV7aqPp0MM3ppa61HZdbJbgsUfXt-mKnAWz7nB4zAF5fbh_0U90Mnt81uMJjQfXnipecJczWXnnbWBohZCG2yoY62xZqToXaJxEb6Xj0hUVBm6kCApNKH1RyAG5-duNiLjYprgxab84PiZ_ARC7X00</recordid><startdate>201311</startdate><enddate>201311</enddate><creator>Xin Zhang</creator><creator>Okuma, Yasuyuki</creator><creator>Po-Hung Chen</creator><creator>Ishida, Koichi</creator><creator>Ryu, Yoshikatsu</creator><creator>Watanabe, Kazumori</creator><creator>Sakurai, Takayasu</creator><creator>Takamiya, Makoto</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201311</creationdate><title>A 0.6-V input 94% peak efficiency CCM/DCM digital buck converter in 40-nm CMOS with dual-mode-body-biased zero-crossing detector</title><author>Xin Zhang ; Okuma, Yasuyuki ; Po-Hung Chen ; Ishida, Koichi ; Ryu, Yoshikatsu ; Watanabe, Kazumori ; Sakurai, Takayasu ; Takamiya, Makoto</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-7151c4038dcdbf0eb223a1b8fabcb687942eac3edb3c13c58ef1a32f7eaf6d553</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Clocks</topic><topic>CMOS integrated circuits</topic><topic>Detectors</topic><topic>Inductors</topic><topic>Logic gates</topic><topic>Pulse width modulation</topic><topic>Voltage control</topic><toplevel>online_resources</toplevel><creatorcontrib>Xin Zhang</creatorcontrib><creatorcontrib>Okuma, Yasuyuki</creatorcontrib><creatorcontrib>Po-Hung Chen</creatorcontrib><creatorcontrib>Ishida, Koichi</creatorcontrib><creatorcontrib>Ryu, Yoshikatsu</creatorcontrib><creatorcontrib>Watanabe, Kazumori</creatorcontrib><creatorcontrib>Sakurai, Takayasu</creatorcontrib><creatorcontrib>Takamiya, Makoto</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Xin Zhang</au><au>Okuma, Yasuyuki</au><au>Po-Hung Chen</au><au>Ishida, Koichi</au><au>Ryu, Yoshikatsu</au><au>Watanabe, Kazumori</au><au>Sakurai, Takayasu</au><au>Takamiya, Makoto</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 0.6-V input 94% peak efficiency CCM/DCM digital buck converter in 40-nm CMOS with dual-mode-body-biased zero-crossing detector</atitle><btitle>2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)</btitle><stitle>ASSCC</stitle><date>2013-11</date><risdate>2013</risdate><spage>45</spage><epage>48</epage><pages>45-48</pages><isbn>1479902772</isbn><isbn>9781479902774</isbn><eisbn>1479902802</eisbn><eisbn>9781479902804</eisbn><abstract>A 0.6-V input, 0.3-0.55V output buck converter is developed in 40-nm CMOS, for low-voltage low-power wireless sensor network systems. The buck converter is able to automatically select DCM or CCM operation, therefore improving the power efficiency and enlarging the output current range, by virtue of the proposed low-power CCM/DCM controller. A dual-mode-body-biased (DMBB) (forward body bias &amp; zero body bias) low-voltage zero-crossing detector is designed to enable DCM operation with both low supply voltage and normal supply voltage. The proposed buck converter achieves a peak efficiency of 94% with an output current range of 50μA to 10mA. Thanks to the DCM operation, the efficiency at an output current of 100μA is improved by 20% and 9%, with an output voltage of 0.35V and 0.5V, respectively.</abstract><pub>IEEE</pub><doi>10.1109/ASSCC.2013.6690978</doi><tpages>4</tpages></addata></record>
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Clocks
CMOS integrated circuits
Detectors
Inductors
Logic gates
Pulse width modulation
Voltage control
title A 0.6-V input 94% peak efficiency CCM/DCM digital buck converter in 40-nm CMOS with dual-mode-body-biased zero-crossing detector
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-29T02%3A57%3A53IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%200.6-V%20input%2094%25%20peak%20efficiency%20CCM/DCM%20digital%20buck%20converter%20in%2040-nm%20CMOS%20with%20dual-mode-body-biased%20zero-crossing%20detector&rft.btitle=2013%20IEEE%20Asian%20Solid-State%20Circuits%20Conference%20(A-SSCC)&rft.au=Xin%20Zhang&rft.date=2013-11&rft.spage=45&rft.epage=48&rft.pages=45-48&rft.isbn=1479902772&rft.isbn_list=9781479902774&rft_id=info:doi/10.1109/ASSCC.2013.6690978&rft.eisbn=1479902802&rft.eisbn_list=9781479902804&rft_dat=%3Cieee_6IE%3E6690978%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i175t-7151c4038dcdbf0eb223a1b8fabcb687942eac3edb3c13c58ef1a32f7eaf6d553%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6690978&rfr_iscdi=true