Design of low power comparator circuit based on reversible logic technology

In this paper, a new 4×4 reversible logic gate named "PR" (Pallavi-Raman) gate has been proposed for application in low power comparator design. Based on PR gate, a four bi t reversible comparator circuit has been designed and was found that the proposed design is better in terms of garbag...

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Main Authors: Shukla, H. P., Rao, A. G., Mall, Pallavi
Format: Conference Proceeding
Language:English
Subjects:
Bismuth
Comparator
Constant Input
Delays
Garbage Output
Heating
Logic circuits
Logic gates
Optimization
Power demand
Quantum Cost
Reversible Logic Technology (RLT)
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Rao, A. G.
Mall, Pallavi
description In this paper, a new 4×4 reversible logic gate named "PR" (Pallavi-Raman) gate has been proposed for application in low power comparator design. Based on PR gate, a four bi t reversible comparator circuit has been designed and was found that the proposed design is better in terms of garbage outputs, no. of reversible gates used, quantum cost and no. of constants inputs than previous designs. PR gate can also be used to perform various operations like, subtraction, copier AND, NAND, XOR, XNOR and NOT gate, thus working as a Reversible Logic Universal Gate.
doi_str_mv 10.1109/ICETACS.2013.6691385
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Bismuth
Comparator
Constant Input
Delays
Garbage Output
Heating
Logic circuits
Logic gates
Optimization
Power demand
Quantum Cost
Reversible Logic Technology (RLT)
title Design of low power comparator circuit based on reversible logic technology
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