A 60 GHz CMOS power amplifier with modified pre-distortion linearizer

This paper proposes a new pre-distortion linearizer for CMOS power amplifier (PA) to improve the performance of the output 1-dB compression power and power added efficiency at 1-dB compression power. By adopting the proposed pre-distortion linearizer, a 60 GHz cascode PA with 13.7-dBm 1-dB compressi...

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Bibliographic Details
Main Authors: Yu-Chung Hsu, Kun-Yao Kao, Jui-Chih Kao, Tzung-Chuen Tsai, Kun-You Lin
Format: Conference Proceeding
Language:English
Subjects:
60 GHz
CMOS
CMOS integrated circuits
CMOS process
Delay lines
Gain
Power amplifiers
Power generation
pre-distortion linearizer
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Summary:This paper proposes a new pre-distortion linearizer for CMOS power amplifier (PA) to improve the performance of the output 1-dB compression power and power added efficiency at 1-dB compression power. By adopting the proposed pre-distortion linearizer, a 60 GHz cascode PA with 13.7-dBm 1-dB compression power (P 1dB ) and 14.3% power added efficiency (PAE) at P 1dB is demonstrated. The chip size is 0.55 × 0.45 mm 2 including all testing pads.
ISSN:0149-645X
2576-7216
DOI:10.1109/MWSYM.2013.6697359