Performance and process characteristic of glass interposer with through-glass-via(TGV)

• Main Authors: Chun-Hsien Chien, Hsun Yu, Ching-Kuan Lee, Yu-Min Lin, Ren-Shin Cheng, Chau-Jie Zhan, Peng-Shu Chen, Chang-Chih Liu, Chao-Kai Hsu, Hsiang-Hung Chang, Huan-Chun Fu, Yuan-Chang Lee, Wen-Wei Shen, Cheng-Ta Ko, Wei-Chung Lo, Lu, Yung Jean
• Format: Conference Proceeding
• Language: English
• Subjects: 3DIC; Bonding; electrical design; formatting; Glass; glass assembly; glass interposer; glass stacking; Impedance; Insertion loss; Scattering parameters; Silicon; TGV; through glass via; Topology
• DOI: 10.1109/3DIC.2013.6702380

Primary approach of 3DIC packaging usually adopts organic substrates or silicon interposer as the intermedium between multi-integrated circuits (ICs) and printed circuit board. Current organic substrates face the limitations in poor dimensional stability, trace density and CTE mismatch to silicon. Silicon interposer is a good solution for high-pin-count ICs and high performance applications based on the mature Si technology of advance via formation and fine line Cu damascene multilevel interconnection process, but silicon interposer is limited by high cost. Glass is proposed as ideal interposer material due to high resistivity, low dielectric constant, low insertion loss and adjustable coefficient of thermal expansion (CTE) for the 3DIC assembly integration and most importantly low cost solution, [1-4]. The main focus of this paper is on (a) TGV electrical design, simulation and characterization, (b) wafer level integration in TGV formation, two RDL on the front-side, one RDL on the backside and polymer-based PBO for the passivation, (c) assembly process of silicon chip stack on the glass interposer with Kelvin resistance measurement. The glass interposer was assessed to have excellent electrical characteristics and is potentially to be applied for 3D product applications.