Energy Efficient Last Level Caches via Last Read/Write Prediction

The size of the Last Level Caches (LLC) in multi-core architectures is increasing, and so is their power consumption. However, most of this power is wasted on unused or invalid cache lines. For dirty cache lines, the LLC waits until the line is evicted to be written back to memory. Hence, dirty line...

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Bibliographic Details
Main Authors: Alves, Marco A. Z., Villavieja, Carlos, Diener, Matthias, Navaux, Philippe O. A.
Format: Conference Proceeding
Language:English
Subjects:
Accuracy
Benchmark testing
Cache Memory
Computer Architecture
Dead line
Energy consumption
Energy Efficiency
History
Logic gates
Prefetching
Radiation detectors
Write-back predictor
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Description
Summary:The size of the Last Level Caches (LLC) in multi-core architectures is increasing, and so is their power consumption. However, most of this power is wasted on unused or invalid cache lines. For dirty cache lines, the LLC waits until the line is evicted to be written back to memory. Hence, dirty lines compete for the memory bandwidth with read requests (prefetch and demand), increasing pressure on the memory controller. This paper proposes a Dead Line and Early Write-Back Predictor (DEWP) to improve the energy efficiency of the LLC. DEWP early evicts dead cache lines with an average accuracy of 94%, and only 2% false positives. DEWP also allows scheduling of dirty lines for early eviction, allowing earlier write-backs. Using DEWP over a set of single and multi-threaded benchmarks, we obtain an average of 61% static energy savings, while maintaining the performance, for both inclusive and non-inclusive LLCs.
ISSN:1550-6533
2643-3001
DOI:10.1109/SBAC-PAD.2013.12