Threshold voltage optimization in a 22nm High-k/Salicide PMOS device

• Main Authors: Maheran, A. H. Afifah, Menon, P. S., Ahmad, I., Yusoff, Z.
• Format: Conference Proceeding
• Language: English
• Subjects: 22 nm gate length PMOS; Annealing; High K dielectric materials; high-k/SALICIDE; Logic gates; MOS devices; Noise; Silicides; Taguchi Method; Threshold voltage
• DOI: 10.1109/RSM.2013.6706489

In this article, we examine the effect of four process parameters and two noise parameters on the threshold voltage (V th ) of a 22nm gate length PMOS device. The gate of the device uses titanium dioxide (TiO 2 ) as the high permittivity material (high-k) layer to replace the traditional silicon dioxide (SiO 2 ) dielectric layer. While the polysilicon (poly-Si) which is also known as self-aligned silicide (SALICIDE) layer, is deposited on top of the high-k dielectric layer and is used to reduce the gate electrode resistance. The virtual fabrication device was designed using the ATHENA and electrical characterization was simulated using ATLAS. These two simulators were combined with the L9 Taguchi's experimental design to aid in the design and optimization of the process parameters for a total of 36 simulation runs. The objective is to minimize the variance in V th using Taguchi's nominal-the-best signal-to-noise ratio (SNR) analysis. Analysis of the mean (ANOM) was used to determine the best settings for the process parameters while Analysis of variance (ANOVA) was used to reduce the variability of V th . The results show that the V th values with the least variance is -0.289 V ± 12.7% which is well within the prediction by the International Technology Roadmap for Semiconductors (ITRS) 2011.