Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2014-12, Vol.22 (12), p.2561-2570
• Main Authors: Botman, Francois, Bol, David, Legat, Jean-Didier, Roy, Kaushik
• Format: Article
• Language: English
• Subjects: Accelerator architectures; Circuits; Clocks; CMOS integrated circuits; Delays; Detectors; Electronics industry; low-power electronics; near-threshold/subthreshold logic; Registers; Synchronization; Transistors; ultralow power; ultralow voltage; variability mitigation
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2013.2297176

With the advent of mobile electronics requiring ever more computing power from a limited energy supply, there is a need for efficient systems capable of maximizing this ratio. Architectural enhancements must therefore be designed to enable high performance, all the while maintaining the power advantage. The technique proposed in this paper allows the acceleration of combinatorial circuits beyond the performance generally achievable by conventional synthesis and timing closure, by exploiting the data-dependent delay variations inherent in such circuits. Through the automatic insertion of transition detectors within the target circuit, the progress of operations underway can be monitored and prematurely completed, thereby increasing the operation speed from the worst toward the average case. In addition, a synthesis flow is proposed to increase the proportion of fast paths, thereby increasing the technique's impact. The proposed technique was applied automatically to a series of benchmark circuits, and the synthesis results show it to achieve good performance, with an average increase of 29% over conventional synthesis, for an average energy increase of {