2nd Generation dual-channel optimization with cSiGe for 22nm HP technology and beyond

In this paper we report on a comprehensive study of Silicon-Germanium channel (cSiGe) physics, layout effects and impact on device performance. This work demonstrates a 2 nd generation of dual channel technology, which meets the 22nm high performance technology (HP) requirement. Modeling and simulat...

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Main Authors: Ortolland, C., Jaeger, D., Mcardle, T. J., Dewan, C., Robison, R. R., Zhao, K., Cai, J., Chang, P., Liu, Y., Varadarajan, V., Wang, G., Chou, A. I., Ioannou, D. P., Oldiges, P., Agnello, P., Narasimha, S., Narayanan, V., Freeman, G.
Format: Conference Proceeding
Language:English
Subjects:
Junctions
Logic gates
Optimization
Performance evaluation
Random access memory
Silicon germanium
Strain
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Summary:In this paper we report on a comprehensive study of Silicon-Germanium channel (cSiGe) physics, layout effects and impact on device performance. This work demonstrates a 2 nd generation of dual channel technology, which meets the 22nm high performance technology (HP) requirement. Modeling and simulation are used to optimize the process to obtain a 10% Short Channel Effect (SCE) improvement and an overall 20% performance enhancement. This 2 nd generation high performance dual channel process has been integrated into a manufacturable and yieldable technology, thereby providing a solid platform for introduction of SiGe FinFet technology.
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2013.6724594