Loading…
Exploring the design of ultra-low energy global interconnects based on spin-torque switches
Emerging spin-torque phenomena, like Spin Hall Effect (SHE), may lead to high-speed, low-voltage current-mode switches based on nano-scale magnets. In this work we propose and analyze the application of such spin-torque switches in the design of energy-efficient and high-performance current-mode on-...
Saved in:
Main Authors: | , , |
---|---|
Format: | Conference Proceeding |
Language: | English |
Subjects: | |
Online Access: | Request full text |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
cited_by | |
---|---|
cites | |
container_end_page | 32.6.4 |
container_issue | |
container_start_page | 32.6.1 |
container_title | |
container_volume | |
creator | Sharad, Mrigank Xuanyao Fong Roy, Kaushik |
description | Emerging spin-torque phenomena, like Spin Hall Effect (SHE), may lead to high-speed, low-voltage current-mode switches based on nano-scale magnets. In this work we propose and analyze the application of such spin-torque switches in the design of energy-efficient and high-performance current-mode on-chip global-interconnects. Simulations show the possibility of achieving up to two order of magnitude higher energy-efficiency as compared to conventional CMOS techniques, for optimal spin-device parameters. A case study for on-chip MRAM cache simulation shows ~90% reduction in energy for on-chip memory access, using the proposed interconnect design. |
doi_str_mv | 10.1109/IEDM.2013.6724739 |
format | conference_proceeding |
fullrecord | <record><control><sourceid>proquest_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_6724739</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6724739</ieee_id><sourcerecordid>1692407890</sourcerecordid><originalsourceid>FETCH-LOGICAL-i123t-4e22cfaf486962bfe48df694b9d05b7f7b8e6770deaccf30a61ff9084f77074e3</originalsourceid><addsrcrecordid>eNotkEFLAzEYRKMo2FZ_gHjJ0cvWJJtNNkepVQsVLwqChyW7-2UbSZOapNT-ewvtaWB4vIFB6JaSKaVEPSzmT29TRmg5FZJxWaozNKZcKsVKIsg5GjFaiYJQ-XWBRoSKsqCK1ldonNIPIUxWqhqh7_nfxoVo_YDzCnAPyQ4eB4O3LkdduLDD4CEOezy40GqHrc8Qu-A9dDnhVifocfA4bawvcoi_W8BpZ3O3gnSNLo12CW5OOUGfz_OP2WuxfH9ZzB6XhaWszAUHxjqjDa-FEqw1wOveCMVb1ZOqlUa2NQgpSQ-660xJtKDGKFJzcyglh3KC7o_eTQyH_ZSbtU0dOKc9hG1qqFCME1krckDvjqgFgGYT7VrHfXP6r_wHkH1j5w</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype><pqid>1692407890</pqid></control><display><type>conference_proceeding</type><title>Exploring the design of ultra-low energy global interconnects based on spin-torque switches</title><source>IEEE Xplore All Conference Series</source><creator>Sharad, Mrigank ; Xuanyao Fong ; Roy, Kaushik</creator><creatorcontrib>Sharad, Mrigank ; Xuanyao Fong ; Roy, Kaushik</creatorcontrib><description>Emerging spin-torque phenomena, like Spin Hall Effect (SHE), may lead to high-speed, low-voltage current-mode switches based on nano-scale magnets. In this work we propose and analyze the application of such spin-torque switches in the design of energy-efficient and high-performance current-mode on-chip global-interconnects. Simulations show the possibility of achieving up to two order of magnitude higher energy-efficiency as compared to conventional CMOS techniques, for optimal spin-device parameters. A case study for on-chip MRAM cache simulation shows ~90% reduction in energy for on-chip memory access, using the proposed interconnect design.</description><identifier>ISSN: 0163-1918</identifier><identifier>EISSN: 2156-017X</identifier><identifier>EISBN: 1479923060</identifier><identifier>EISBN: 9781479923069</identifier><identifier>DOI: 10.1109/IEDM.2013.6724739</identifier><language>eng</language><publisher>IEEE</publisher><subject>CMOS ; Energy use ; High speed ; Integrated circuit interconnections ; Interconnections ; Magnetic domains ; Magnetic tunneling ; Magnetoresistive random access memory ; Optimization ; Perpendicular magnetic anisotropy ; Sensors ; Simulation ; Switches ; System-on-chip</subject><ispartof>2013 IEEE International Electron Devices Meeting, 2013, p.32.6.1-32.6.4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6724739$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,780,784,789,790,23929,23930,25139,27923,27924,54554,54931</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6724739$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Sharad, Mrigank</creatorcontrib><creatorcontrib>Xuanyao Fong</creatorcontrib><creatorcontrib>Roy, Kaushik</creatorcontrib><title>Exploring the design of ultra-low energy global interconnects based on spin-torque switches</title><title>2013 IEEE International Electron Devices Meeting</title><addtitle>IEDM</addtitle><description>Emerging spin-torque phenomena, like Spin Hall Effect (SHE), may lead to high-speed, low-voltage current-mode switches based on nano-scale magnets. In this work we propose and analyze the application of such spin-torque switches in the design of energy-efficient and high-performance current-mode on-chip global-interconnects. Simulations show the possibility of achieving up to two order of magnitude higher energy-efficiency as compared to conventional CMOS techniques, for optimal spin-device parameters. A case study for on-chip MRAM cache simulation shows ~90% reduction in energy for on-chip memory access, using the proposed interconnect design.</description><subject>CMOS</subject><subject>Energy use</subject><subject>High speed</subject><subject>Integrated circuit interconnections</subject><subject>Interconnections</subject><subject>Magnetic domains</subject><subject>Magnetic tunneling</subject><subject>Magnetoresistive random access memory</subject><subject>Optimization</subject><subject>Perpendicular magnetic anisotropy</subject><subject>Sensors</subject><subject>Simulation</subject><subject>Switches</subject><subject>System-on-chip</subject><issn>0163-1918</issn><issn>2156-017X</issn><isbn>1479923060</isbn><isbn>9781479923069</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotkEFLAzEYRKMo2FZ_gHjJ0cvWJJtNNkepVQsVLwqChyW7-2UbSZOapNT-ewvtaWB4vIFB6JaSKaVEPSzmT29TRmg5FZJxWaozNKZcKsVKIsg5GjFaiYJQ-XWBRoSKsqCK1ldonNIPIUxWqhqh7_nfxoVo_YDzCnAPyQ4eB4O3LkdduLDD4CEOezy40GqHrc8Qu-A9dDnhVifocfA4bawvcoi_W8BpZ3O3gnSNLo12CW5OOUGfz_OP2WuxfH9ZzB6XhaWszAUHxjqjDa-FEqw1wOveCMVb1ZOqlUa2NQgpSQ-660xJtKDGKFJzcyglh3KC7o_eTQyH_ZSbtU0dOKc9hG1qqFCME1krckDvjqgFgGYT7VrHfXP6r_wHkH1j5w</recordid><startdate>20131201</startdate><enddate>20131201</enddate><creator>Sharad, Mrigank</creator><creator>Xuanyao Fong</creator><creator>Roy, Kaushik</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>20131201</creationdate><title>Exploring the design of ultra-low energy global interconnects based on spin-torque switches</title><author>Sharad, Mrigank ; Xuanyao Fong ; Roy, Kaushik</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i123t-4e22cfaf486962bfe48df694b9d05b7f7b8e6770deaccf30a61ff9084f77074e3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>CMOS</topic><topic>Energy use</topic><topic>High speed</topic><topic>Integrated circuit interconnections</topic><topic>Interconnections</topic><topic>Magnetic domains</topic><topic>Magnetic tunneling</topic><topic>Magnetoresistive random access memory</topic><topic>Optimization</topic><topic>Perpendicular magnetic anisotropy</topic><topic>Sensors</topic><topic>Simulation</topic><topic>Switches</topic><topic>System-on-chip</topic><toplevel>online_resources</toplevel><creatorcontrib>Sharad, Mrigank</creatorcontrib><creatorcontrib>Xuanyao Fong</creatorcontrib><creatorcontrib>Roy, Kaushik</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sharad, Mrigank</au><au>Xuanyao Fong</au><au>Roy, Kaushik</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Exploring the design of ultra-low energy global interconnects based on spin-torque switches</atitle><btitle>2013 IEEE International Electron Devices Meeting</btitle><stitle>IEDM</stitle><date>2013-12-01</date><risdate>2013</risdate><spage>32.6.1</spage><epage>32.6.4</epage><pages>32.6.1-32.6.4</pages><issn>0163-1918</issn><eissn>2156-017X</eissn><eisbn>1479923060</eisbn><eisbn>9781479923069</eisbn><abstract>Emerging spin-torque phenomena, like Spin Hall Effect (SHE), may lead to high-speed, low-voltage current-mode switches based on nano-scale magnets. In this work we propose and analyze the application of such spin-torque switches in the design of energy-efficient and high-performance current-mode on-chip global-interconnects. Simulations show the possibility of achieving up to two order of magnitude higher energy-efficiency as compared to conventional CMOS techniques, for optimal spin-device parameters. A case study for on-chip MRAM cache simulation shows ~90% reduction in energy for on-chip memory access, using the proposed interconnect design.</abstract><pub>IEEE</pub><doi>10.1109/IEDM.2013.6724739</doi></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 0163-1918 |
ispartof | 2013 IEEE International Electron Devices Meeting, 2013, p.32.6.1-32.6.4 |
issn | 0163-1918 2156-017X |
language | eng |
recordid | cdi_ieee_primary_6724739 |
source | IEEE Xplore All Conference Series |
subjects | CMOS Energy use High speed Integrated circuit interconnections Interconnections Magnetic domains Magnetic tunneling Magnetoresistive random access memory Optimization Perpendicular magnetic anisotropy Sensors Simulation Switches System-on-chip |
title | Exploring the design of ultra-low energy global interconnects based on spin-torque switches |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T07%3A50%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Exploring%20the%20design%20of%20ultra-low%20energy%20global%20interconnects%20based%20on%20spin-torque%20switches&rft.btitle=2013%20IEEE%20International%20Electron%20Devices%20Meeting&rft.au=Sharad,%20Mrigank&rft.date=2013-12-01&rft.spage=32.6.1&rft.epage=32.6.4&rft.pages=32.6.1-32.6.4&rft.issn=0163-1918&rft.eissn=2156-017X&rft_id=info:doi/10.1109/IEDM.2013.6724739&rft.eisbn=1479923060&rft.eisbn_list=9781479923069&rft_dat=%3Cproquest_CHZPO%3E1692407890%3C/proquest_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i123t-4e22cfaf486962bfe48df694b9d05b7f7b8e6770deaccf30a61ff9084f77074e3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=1692407890&rft_id=info:pmid/&rft_ieee_id=6724739&rfr_iscdi=true |