A power gating GALS interface implementation

• Main Authors: Rajakumari, A., Sharma, N. S. Murthy, Kishore, K. Lal, Petta, Vasantha Kumar
• Format: Conference Proceeding
• Language: English
• Subjects: 4-Phase handshking; Asia; Asynchronous Wrappers; Clock Gating; Clocks; Globally asynchronous locally synchronous (GALS); Microelectronics; Petri Nets; Power Gating; Relative Timing; SignaI Transition Graph (STG); Switches; Synchronization; System-on-chip
• ISSN: 2159-2144; 2159-2160
• DOI: 10.1109/PrimeAsia.2013.6731174

In today's nanometric VLSI designs achieving both power and performance targets is the top most priority for design closure. Globally asynchronous locally synchronous (GALS) architectures can offer less dynamic power and improved performance due to absence of global clock. In GALS SoC architectures each synchronous blocks runs on their local clocks. Synchronous blocks communicate with each other by pausing their local clocks using an asynchronous interface which is implemented using various handshake protocols. However any synchronous block which has to wait long time for data from another block need to be in idle state and as a result will dissipate significant leakage power in nanometric designs. Power gating is an effective technique to reduce leakage power of an idle circuit in synchronous designs. However implementing such power gating interface in GALS architecture is a challenge in the absence of clock. Thus to reduce the leakage power in ideal blocks which are waiting for the data, a new GALS wrapper interface was proposed which can generate power gating sequence. To corroborate the proposed interface a GALS 8051 was implemented using Synopsys SAED 90 nm libraries. The power gating sequence of 8051 asynchronous wrappers are used to gate the power of Random Access Memory (RAM) block while Arithmetic Logic Unit (ALU) block is busy in doing arithmetic operations. The experimental results show a 30% reduction in leakage power of RAM block due to power gating.