Parallel and configurable turbo decoder implementation for 3GPP-LTE

An FPGA implementation of a highly parallel and configurable architecture for turbo decoding, compliant with the 3GPP-LTE standard is presented. This architecture can be integrated in reconfigurable platforms for software defined radio applications. A novel combination of the next iteration initiali...

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Bibliographic Details
Main Authors: Gonzalez-Perez, Luis F., Yllescas-Calderon, Lennin C., Parra-Michel, R.
Format: Conference Proceeding
Language:English
Subjects:
3GPP-LTE
Computer architecture
Decoding
Hardware
Iterative decoding
MAP decoder
Measurement
parallel turbo decoding
QPP interleaving
Software Defined Radio
Throughput
Turbo codes
VLSI
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Description
Summary:An FPGA implementation of a highly parallel and configurable architecture for turbo decoding, compliant with the 3GPP-LTE standard is presented. This architecture can be integrated in reconfigurable platforms for software defined radio applications. A novel combination of the next iteration initialization method and the parallel and sliding window techniques is used in the MAP algorithm. This allows high throughput and reduced storage requirements, as compared to other solutions. Synthesis results on Altera FPGAs show that this architecture can reach 337.6 Mbps at 8 decoding iterations.
ISSN:2325-6532
2640-0472
DOI:10.1109/ReConFig.2013.6732316