Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOS

Quantum mechanical principles that govern the basic laws of physics increasingly limit CMOS operation with transistor scaling. Traditional logic based CMOS circuits cannot achieve ultra-low power levels due to heat dissipated for a single bit loss of information as represented by the Landauer barrie...

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Bibliographic Details
Main Authors: Morrison, Matthew, Ranganathan, Nagarajan
Format: Conference Proceeding
Language:English
Subjects:
Adiabatic flow
Adiabatic Logic
Circuits
CMOS
CMOS integrated circuits
Computer simulation
Design engineering
Forward Body Biasing
Integrated circuit modeling
Integrated circuits
Inverters
Logic
Logic gates
Power demand
Reduction
Reversible Logic
Semiconductor device modeling
Transistors
Very large scale integration
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Summary:Quantum mechanical principles that govern the basic laws of physics increasingly limit CMOS operation with transistor scaling. Traditional logic based CMOS circuits cannot achieve ultra-low power levels due to heat dissipated for a single bit loss of information as represented by the Landauer barrier. Reversible logic is a promising computing paradigm towards realization of ultra-low power computing circuits. Reducing average and peak power consumption is an effective strategy for mitigation of side-channel attacks, such as Differential Power Analysis. We present designs of Forward Body Biased Adiabatic Logic for reduction of average, peak, and differential power. HSPICE simulations with predictive 22nm technology are used to analyze performance metrics and exhaustive simulation results are presented for various reversible CMOS designs. Average power is improved upon by up to 91%, the peak power by up to 96%, and the differential power is improved by up to a factor of 128.57.
ISSN:1063-9667
2380-6923
DOI:10.1109/VLSID.2014.88