Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator

• Published in: IEEE journal of solid-state circuits 2014-03, Vol.49 (3), p.657-672
• Main Authors: Kim, WooSeok, Park, Jaejin, Park, Hojin, Jeong, Deog-Kyoon
• Format: Article
• Language: English
• Subjects: All-digital PLL; automatic placement and routing (auto P&R); cell-based; Clocks; Computer architecture; DCO linearity; dual-loop PLL; Jitter; long-term jitter; Microprocessors; Phase locked loops; Phase noise; pixel clock generator (PCG); Ring oscillators; synthesizable PLL
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2014.2298455

This paper presents a dual-loop ADPLL suitable for video pixel clock generation. The dual-loop architecture where a fast subloop works as a DCO inside a main loop is chosen since it can efficiently suppress the ring oscillator phase noise. In order to satisfy a wide tuning range and fine resolution requirements in the pixel clock PLL, the TDC and DCO with two-step and bottom-up control are employed. An s-domain model is utilized to tune the loop parameters so that the dual-loop PLL has the optimum jitter performance. The measurement results match well with the proposed s-domain model and clearly show the effectiveness of the dual loop in suppressing the phase noise of the DCO. We propose a new cell-based layout technique to avoid performance degradation during automatic placement and routing, which is compatible with the conventional digital design environment. A chip that occupies 0.032 mm 2 has been fabricated in the 28-nm CMOS technology. The synthesized DCO shows 1.7-LSB DNL which is close to a full-custom layout. The rms integrated jitter is only 15 ps at 250 MHz, even though PLL operates at the extremely low input frequency of 100 kHz. Power consumption is 3.1 mW at 250 MHz with a 1.0-V supply.