Diagnosis and Layout Aware (DLA) Scan Chain Stitching

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2015-03, Vol.23 (3), p.466-479
• Main Authors: Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Weipin Changchien, Daw-Ming Lee, Ji-Jan Chen, Eruvathi, Sandeep C., Kumara, Kartik K., Liu, Charles, Sam Pan
• Format: Article
• Language: English
• Subjects: Automatic test pattern generation; Circuit faults; Fault diagnosis; Industries; Layout; Routing; scan chain stitching; sensitive cell; Simulated annealing
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2014.2313563

Without appropriate stitching of scan chains, even with good diagnosis algorithm and diagnostic pattern generation, the chain diagnostic resolution may still be bad. In this paper, we propose a novel pattern-independent diagnosis and layout aware (DLA) scan chain stitching method: 1) the resolution is improved by increasing and properly distributing the sensitive scan cells, which can capture useful diagnostic information under both single- and multiple-fault situations; and 2) the scan cell layout placement is taken into account to reduce routing overhead and hence preserve the chip performance. Experiments using two different techniques to diagnose ISCAS'89/ITC'99 benchmark circuits with/without embedded scan compaction show the effectiveness of the proposed method in improving the diagnostic resolution. Impacts on chip performance, embedded scan compaction, transition fault coverage, and test power dissipation are negligible. The proposed method is also successfully applied to an industry circuit manufactured with 20-nm technology. The silicon results show 7× average resolution improvement comparing to without using the DLA scan chain stitching.