Efficient SMT-based ATPG for interconnect open defects

Interconnect opens are known to be one of the predominant defects in nanoscale technologies. However, automatic test pattern generation for open faults is challenging, because of their rather unstable behaviour and the numerous electric parameters which need to be considered. Thus, most approaches t...

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Bibliographic Details
Main Authors: Erb, Dominik, Scheibler, Karsten, Sauer, Matthias, Becker, Bernd
Format: Conference Proceeding
Language:English
Subjects:
ATPG
Automatic test pattern generation
Capacitance
Circuit faults
Couplings
Integrated circuit interconnections
Integrated circuit modeling
Interconnect opens
Logic gates
SMT
test generation
unknown values
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Summary:Interconnect opens are known to be one of the predominant defects in nanoscale technologies. However, automatic test pattern generation for open faults is challenging, because of their rather unstable behaviour and the numerous electric parameters which need to be considered. Thus, most approaches try to avoid accurate modeling of all constraints and use simplified fault models in order to detect as many faults as possible or make assumptions which decrease both complexity and accuracy. This paper presents a new SMT-based approach which for the first time supports the Robust Enhanced Aggressor Victim model without restrictions and handles oscillations. It is combined with the first open fault simulator fully supporting the Robust Enhanced Aggressor Victim model and thereby accurately considering unknown values. Experimental results show the high efficiency of the new method outperforming previous approaches by up to two orders of magnitude.
ISSN:1530-1591
1558-1101
DOI:10.7873/DATE.2014.138