Bit-Flipping Scan - A unified architecture for fault tolerance and offline test

• Main Authors: Imhof, Michael E., Wunderlich, Hans-Joachim
• Format: Conference Proceeding
• Language: English
• Subjects: ATPG; Bit-Flipping Scan; Circuit faults; Compaction; Computer architecture; Fault tolerance; Fault tolerant systems; Latches; Logic gates; Registers; Satisfiability; Test
• ISSN: 1530-1591; 1558-1101
• DOI: 10.7873/DATE.2014.206

Test is an essential task since the early days of digital circuits. Every produced chip undergoes at least a production test supported by on-chip test infrastructure to reduce test cost. Throughout the technology evolution fault tolerance gained importance and is now necessary in many applications to mitigate soft errors threatening consistent operation. While a variety of effective solutions exists to tackle both areas, test and fault tolerance are often implemented orthogonally, and hence do not exploit the potential synergies of a combined solution. The unified architecture presented here facilitates fault tolerance and test by combining a checksum of the sequential state with the ability to flip arbitrary bits. Experimental results confirm a reduced area overhead compared to a orthogonal combination of classical test and fault tolerance schemes. In combination with heuristically generated test sequences the test application time and test data volume are reduced significantly.