An interference miss isolation mechanism based on skewed mapping for shared cache in Chip Multiprocessors

Inter-thread or intra-thread interference misses may be incurred due to the conflict among different threads when the least-recently-used (LRU) victim candidate is evicted from the shared last level cache in Chip Multiprocessors (CMP). To alleviate this problem, an interference miss isolation mechan...

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Bibliographic Details
Main Authors: Anwen Huang, Chao Song, Wei Guo, Peng Li, Minxuan Zhang
Format: Conference Proceeding
Language:English
Subjects:
Artificial intelligence
Benchmark testing
Hardware
Interference
Memory management
Program processors
Tiles
Online Access:Request full text
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Summary:Inter-thread or intra-thread interference misses may be incurred due to the conflict among different threads when the least-recently-used (LRU) victim candidate is evicted from the shared last level cache in Chip Multiprocessors (CMP). To alleviate this problem, an interference miss isolation mechanism based on skewed mapping (IMI-SM) is proposed for the shared cache in this paper, which is aimed to mitigate the conflict miss phenomena when the on-chip cache is occupied competitively by multiple threads in CMP. The skewed mapping mechanism in IMI-SM is triggered once an interference miss is predicted. The new incoming data fetched from the off-chip memory can be dynamically placed in an dedicated isolation cache or the cache set which is under light pressure, so the negative impact caused by the interference misses in the shared cache is mitigated effectively. Experimental results based on full system simulator demonstrate that IMI-SM can reduce the interference misses in the shared last level cache to a certain extent, and the system performance is improved significantly with negligible hardware overhead.
ISSN:2162-7541
2162-755X
DOI:10.1109/ASICON.2013.6811977