A reconfigurable floating-point FFT architecture

A novel reconfigurable single-precision floating-point FFT architecture for accelerating scientific computing is proposed in this paper. This architecture implements reconfigurable point FFT. The fully pipelined computing unit is used to speed up the FFT operation. To deal with conflicting access to...

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Bibliographic Details
Main Authors: Chenlu Wu, Wei Cao, Xuegong Zhou, Lingli Wang, Fang Wang, Baodi Yuan
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
Adders
Computer architecture
Delays
Field programmable gate arrays
Hardware
Scientific computing
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Summary:A novel reconfigurable single-precision floating-point FFT architecture for accelerating scientific computing is proposed in this paper. This architecture implements reconfigurable point FFT. The fully pipelined computing unit is used to speed up the FFT operation. To deal with conflicting access to delay unit, the improved method is adopted for temporary data storage, which merely costs additional 0.1% of the total memory resources. Compared with conventional CSD multipliers based implementation, our design with RMCM reduces the number of adders by 33.3% and 64.1% for radix-2 3 and radix-2 4 butterfly units, respectively. The proposed processor has been verified on a XC6VSX475T FPGA chip, with the frequency up to 156MHz. The execution time to calculate 131072-point FFT is 840.2 us at 156MHz. It is nearly six times faster than FFTW 3.3.3 running on an IBM server based on Intel Xeon 16-core 1.87GHz CPU and 64 GB memory.
ISSN:2162-7541
2162-755X
DOI:10.1109/ASICON.2013.6811996