CMOS stress sensor for 3D integrated circuits: Thermo-mechanical effects of Through Silicon Via (TSV) on surrounding silicon

• Main Authors: Ewuame, Komi Atchou, Fiori, Vincent, Inal, Karim, Bouchard, Pierre-Olivier, Gallois-Garreignot, Sébastien, Lionti, Sylvain, Tavernier, Clément, Jaouen, Hervé
• Format: Conference Proceeding
• Language: English
• Subjects: Abstracts; Calibration; CMOS integrated circuits; Q measurement; Silicon; Through-silicon vias
• DOI: 10.1109/EuroSimE.2014.6813808

This work aims at determining thermomechanical stresses induced by annealed copper filled Through Silicon Via (TSV) in single crystalline silicon by using MOS (Metal Oxide Semiconductor) rosette sensors. These sensors were specifically designed and embedded. Through the piezoresistive relations, the stress tensor was evaluated by carrying out electrical measurements on test vehicle. The MOS stress sensors would have been needed to be calibrated: first results of the calibration were obtained however, since they were still partial, they were not used to make the bridge from electric to mechanic quantities. Experimental findings were based on the direct calculation of stresses from electrical measurements data and literature piezoresistive coefficients. In order to get only the TSV contribution and to suppress the manufacturing process variability contribution, an optimization calculation was needed. A finite element approach was also adopted to evaluate numerically the stresses induced by TSV. The stress values obtained from the optimization are in the range of the ones obtained by simulation in the sensor area. Thus, it can be stated that the methodology is relevant, and the results will be confirmed by extracting the true piezoresistive coefficients for the embedded MOS. Once calibration performed, the piezoresistive coefficients should enable getting more accurate stress values. At this stage, the quite good agreement between numerical and experimental results seems promising.