High-parallel architecture for H.264/AVC intra prediction implemented via VLSI

The complicated calculations and data dependency have limited further application of the H.264/ AVC standard for a considerable time. To solve such a problem, here in this paper, a dual-parallel architecture that combines block parallel processing and mode parallel processing is proposed to speed up...

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Bibliographic Details
Main Authors: Jiefeng Guo, Zhixin Yang, Jianwei Zheng, Xiaochao Li, Donghui Guo
Format: Conference Proceeding
Language:English
Subjects:
Computer architecture
Encoding
Equations
H.264/AVC
Hardware Architecture
Hardware
Intra Prediction
Mathematical model
Parallel
Parallel processing
Video coding
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Summary:The complicated calculations and data dependency have limited further application of the H.264/ AVC standard for a considerable time. To solve such a problem, here in this paper, a dual-parallel architecture that combines block parallel processing and mode parallel processing is proposed to speed up the process. Since the improvement of the parallelism will lead to increased consumption of the hardware. a formula sharing method is presented to reduce the hardware cost. The experimental results have shown that, synthesized into a TSMC 0.18 μ m CMOS cell library, the new architecture only requires less than 135 K gates and is able to encode 1080pHD video sequences at 30 frames per second (fps), when running at 136 MHZ.
ISSN:2163-5048
2163-5056
DOI:10.1109/ICASID.2013.6825304