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Integration of ALD barrier and CVD Ru liner for void free PVD Cu reflow process on sub-10nm node technologies
Cu-fill extendability is demonstrated with a novel integration scheme using clustered ALD barrier, CVD Ru liner and PVD Cu dry-fill processes. ALD barrier films were developed and integrated with a 2nm CVD-Ru (replacing the traditional PVD Ta and PVD Cu seed), and a single-step PVD Cu dry-fill proce...
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creator | Yu, K. Oie, T. Hasegawa M. Amano, F. Consiglio, S. Wajda, C. Maekawa, K. Leusink, G. |
description | Cu-fill extendability is demonstrated with a novel integration scheme using clustered ALD barrier, CVD Ru liner and PVD Cu dry-fill processes. ALD barrier films were developed and integrated with a 2nm CVD-Ru (replacing the traditional PVD Ta and PVD Cu seed), and a single-step PVD Cu dry-fill process for bottom-up via and trench fill. Line resistance and barrier integrity data complement the Cu-fill performance. |
doi_str_mv | 10.1109/IITC.2014.6831857 |
format | conference_proceeding |
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Hasegawa M. ; Amano, F. ; Consiglio, S. ; Wajda, C. ; Maekawa, K. ; Leusink, G.</creator><creatorcontrib>Yu, K. ; Oie, T. Hasegawa M. ; Amano, F. ; Consiglio, S. ; Wajda, C. ; Maekawa, K. ; Leusink, G.</creatorcontrib><description>Cu-fill extendability is demonstrated with a novel integration scheme using clustered ALD barrier, CVD Ru liner and PVD Cu dry-fill processes. ALD barrier films were developed and integrated with a 2nm CVD-Ru (replacing the traditional PVD Ta and PVD Cu seed), and a single-step PVD Cu dry-fill process for bottom-up via and trench fill. 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Hasegawa M.</creatorcontrib><creatorcontrib>Amano, F.</creatorcontrib><creatorcontrib>Consiglio, S.</creatorcontrib><creatorcontrib>Wajda, C.</creatorcontrib><creatorcontrib>Maekawa, K.</creatorcontrib><creatorcontrib>Leusink, G.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yu, K.</au><au>Oie, T. Hasegawa M.</au><au>Amano, F.</au><au>Consiglio, S.</au><au>Wajda, C.</au><au>Maekawa, K.</au><au>Leusink, G.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Integration of ALD barrier and CVD Ru liner for void free PVD Cu reflow process on sub-10nm node technologies</atitle><btitle>IEEE International Interconnect Technology Conference</btitle><stitle>IITC</stitle><date>2014-05</date><risdate>2014</risdate><spage>117</spage><epage>120</epage><pages>117-120</pages><issn>2380-632X</issn><eissn>2380-6338</eissn><isbn>9781479950164</isbn><isbn>1479950165</isbn><eisbn>9781479950188</eisbn><eisbn>1479950181</eisbn><abstract>Cu-fill extendability is demonstrated with a novel integration scheme using clustered ALD barrier, CVD Ru liner and PVD Cu dry-fill processes. ALD barrier films were developed and integrated with a 2nm CVD-Ru (replacing the traditional PVD Ta and PVD Cu seed), and a single-step PVD Cu dry-fill process for bottom-up via and trench fill. Line resistance and barrier integrity data complement the Cu-fill performance.</abstract><pub>IEEE</pub><doi>10.1109/IITC.2014.6831857</doi><tpages>4</tpages></addata></record> |
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source | IEEE Xplore All Conference Series |
subjects | Annealing Dielectrics Electrical resistance measurement Metallization Resistance |
title | Integration of ALD barrier and CVD Ru liner for void free PVD Cu reflow process on sub-10nm node technologies |
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