Stacking Signal TSV for Thermal Dissipation in Global Routing for 3-D IC

With no further shrinking of device size, 3-D chip stacking by through-silicon-via (TSV) has been identified as an effective way to achieve better performance in speed and power. However, such solution inevitably encounters challenges in thermal dissipation since stacked dies generate a significant...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2014-07, Vol.33 (7), p.1031-1042
Main Authors: Hsu, Po-Yang, Chen, Hsien-Te, Hwang, TingTing
Format: Article
Language:English
Subjects:
Design engineering
Dissipation
Heat sinks
Heating
Integrated circuits
Mathematical models
Reduction
Routing
Stacking
Steiner trees
Thermal resistance
Three dimensional
Through-silicon vias
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Summary:With no further shrinking of device size, 3-D chip stacking by through-silicon-via (TSV) has been identified as an effective way to achieve better performance in speed and power. However, such solution inevitably encounters challenges in thermal dissipation since stacked dies generate a significant amount of heat per unit volume. We leverage an integrated design methodology of stacked-signal-TSVs to minimize temperature. Based on this structure, a three-stage TSV locating algorithm in global routing is designed. We demonstrate that our results, compared with baseline circuits, have 17% temperature reduction with 3% wiring overhead and no performance loss calculated by 3-D Elmore delay model. Compared with the paper by Cong and Zhang where additional thermal TSVs are inserted, our experimental results have in average 23% less TSVs with the same temperature constraint. Compared with the paper by Pathak and Lim, where movable signal TSVs are relocated to reduce temperature in hotspot regions, our result has 8% more temperature reduction with the same number of signal TSVs.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2014.2307488