Fabrication of High-Performance Poly-Si Thin-Film Transistors With Sub-Lithographic Channel Dimensions

A method for fabrication of tri-gate polycrystalline silicon (poly-Si) transistors with short channel length and width is proposed and demonstrated without employing costly lithographic tools. Specifically, the method employs a spacer formation technique to extend source and drain regions so as to s...

Full description

Saved in:
Bibliographic Details
Published in:Journal of display technology 2014-11, Vol.10 (11), p.966-970
Main Authors: Lee, Ko-Hui, Lin, Horng-Chih, Huang, Tiao-Yuan
Format: Article
Language:English
Subjects:
Channels
Display devices
Drains
Etching
Fabrication
Lithography
Logic gates
Photoresists
Plasmas
poly-Si
Retarding
Semiconductor devices
Spacers
Thin film transistors
Thin films
thin-film transistor (TFT)
tri-gate
Trimming
Voltage measurement
Citations: Items that this one cites
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A method for fabrication of tri-gate polycrystalline silicon (poly-Si) transistors with short channel length and width is proposed and demonstrated without employing costly lithographic tools. Specifically, the method employs a spacer formation technique to extend source and drain regions so as to scale down the channel length below sub-lithographic dimension. Concurrently, the channel width is scaled down below sub-lithographic dimension by using a photoresist (PR) trimming technique. Our results show that the reduction in the planar channel width is essential for suppressing the short-channel effects. Finally, devices with channel length of 120 nm and planar channel width of 110 nm are demonstrated with superior electrical characteristics in terms of small subthreshold swing (146 mV/dec) and low drain-induced-barrier-lowing value (100 mV/V).
ISSN:1551-319X
1558-9323
DOI:10.1109/JDT.2014.2334361